Powertech Technology Inc.

Hiroyuki Fujishima

Shang-Yu Chang-Chien

Shou-Chian Hsu

A chip-middle type fan-out panel-level package (FOPLP) has a routing layer, a polyimide layer formed on the routing layer and having a plurality of pillar openings and a chip opening, a plurality of metal pillars mounted on the routing layer through the corresponding pillar openings, a chip mounted on the first routing layer through the chip opening and a molding compound formed on the polyimide layer to encapsulate the metal pillars and the chip. The polyimide layer is used to control the warpage of the FOPLP. The polyimide layer is formed inside the FOPLP and the chip is directly mounted on the first routing layer through the chip opening, so a height of the FOPLP is not increased when the first PI layer is added.

Chip-middle type fan-out panel-level package and packaging method thereof

A semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer is provided. The insulating layer has an accommodating opening. The chip is disposed in the accommodating opening. The chip has an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface. The thermal interface material is filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface. The re-distribution layer and the heat-dissipating cover are disposed on two side of the insulating layer respectively. The heat-dissipating cover is thermally coupled to the chip through the thermal interface material. The re-distribution layer covers the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.

Growing community of inventors

Hsinchu County, Taiwan

Hiroyuki Fujishima