Shin-etsu Handotai Co., Ltd.

Hirotaka Kurimoto

Ken Sato

Hirokazu Goto

Hiroshi Shikauchi

Masaru Shinomiya

Kazunori Hagimoto

Keitaro Tsuchiya

Shoichi Kobayashi

Fumiaki Maruyama

Naoto Iizuka

Koichi Kosaka

A method of manufacturing an epitaxial wafer having an epitaxial layer on a silicon-based substrate, the method of manufacturing the epitaxial wafer including epitaxially growing a semiconductor layer on the silicon-based substrate after applying terrace processing to an outer peripheral portion of the silicon-based substrate. As a result, the method of manufacturing the epitaxial wafer having the epitaxial layer on the silicon-based substrate in which an epitaxial wafer which is completely free from cracks can be obtained, is provided.

Method of manufacturing epitaxial wafer and silicon-based substrate for epitaxial growth

A method for producing a semiconductor epitaxial wafer, including steps of: fabricating an epitaxial wafer by epitaxially growing a semiconductor layer on a silicon-based substrate; observing the outer edge portion of the fabricated epitaxial wafer; and removing portions in which a crack, epitaxial layer peeling, and a reaction mark observed in the step of observing are present. As a result, a method for producing a semiconductor epitaxial wafer in which a completely crack-free semiconductor epitaxial wafer can be obtained, is provided.

Method for producing semiconductor epitaxial wafer and semiconductor epitaxial wafer

The present invention provides a final polishing method for a silicon single crystal wafer that performs final polishing with a polishing rate being set to 10 nm/min or below at a final polishing step as a final step among a plurality of polishing steps for polishing the silicon single crystal wafer with a polishing slurry being interposed between the silicon single crystal wafer and a polishing pad, and a silicon single crystal wafer subjected to final polishing by this method. Hereby, there can be provided the final polishing method that can obtain a silicon single crystal wafer with less PIDs (Polishing Induced Defects) and the silicon single crystal wafer subjected to final polishing by this method.

Final polishing method for silicon single crystal wafer and silicon single crystal wafer

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Jyoetsu, Japan

Hirotaka Kurimoto