Sony Computer Entertainment Inc.

International Business Machines Corporation

Toshiba America Electronic Components, Inc.

Hiroshi Yoshihara

Sang Hoo Dhong

Osamu Takahashi

Atsushi Hayashi

Takaaki Nakazato

Yoichi Nishino

Shunsaku Tokito

Yuuki Fujiyama

A system and method for testing a memory array are disclosed which may include establishing a stored data vector, including a plurality of data bits, within at least one circuit; applying one or more logical operations on the stored data vector to generate a succession of original data vectors at the at least one circuit; transmitting the succession of original data vectors through a memory array to provide a succession of exercised data vectors; comparing the succession of exercised data vectors to the succession of respective original data vectors; and determining whether the memory array passes or fails based on the comparing step.

Method and apparatus for testing a circuit

Methods and apparatus provide for testing an SRAM cell, the SRAM cell including an anti-parallel storage circuit operable to store a logic high or low value across a true node and a complementary node, where the true node and complementary node are coupled to a true bit line (BLT) and a complementary bit line (BLC), by first and second transistors, respectively, the method including: preventing a write driver circuit from significantly pulling the BLT towards a supply voltage; preventing a pre-charge circuit from significantly pulling the BLT towards the supply voltage; preventing the first transistor from significantly pulling the BLT towards the voltage stored in the SRAM cell; and comparing the voltage of the BLT under the foregoing conditions to a threshold voltage.

Method and apparatus for screening bit line of a static random access memory (SRAM) for excessive leakage current

Methods and apparatus provide for controlling an SRAM memory, the SRAM memory including a plurality of memory cells arranged in an array of rows (word lines) and columns (bit lines), comprising: inverting a state of data for input to one or more columns of the array; and storing the inverted data in one or more memory cells of the one or more columns.

Methods and apparatus for low power SRAM based on stored data

A system and method are disclosed which may include establishing a stored test vector, including a plurality of data bits, within a vector data engine; transmitting the stored test vector to a memory array; performing at least one arithmetic or logical operation upon the stored test vector by a vector data generator within the vector data engine to update the stored test vector; and repeating the steps of transmitting and performing so as to continuously transmit continuously changing stored test vectors to the memory array.

Methods and apparatus for communicating with a target circuit

Methods and apparatus provide for enabling a digital circuit by biasing at least one switch transistor ON such that a voltage potential of a virtual ground node is substantially equal to a voltage potential of a ground node for a power supply to the digital circuit, wherein the digital circuit is implemented using a plurality of transistors in a silicon-on-insulator (SOI) arrangement and at least some of the transistors are referenced to the virtual ground node; and disabling the digital circuit by biasing a gate terminal of the switch transistor below the voltage potential of the ground node.

Methods and apparatus for reducing leakage current in a disabled SOI circuit

Methods and apparatus provide for: testing a static random access memory (SRAM) to obtain performance data on the SRAM; and using the performance data as at least a basis of a identification number.

Growing community of inventors

Round Rock, TX, United States of America

Hiroshi Yoshihara