Renesas Electronics Corporation

Nec Corporation

Nec Electronics Corporation

Hiroshi Yanagigawa

Kazuhisa Mori

Katsumi Eikyu

Taro Moriya

Hiroyoshi Kudou

Akihiro Shimomura

Yasutaka Nakashiba

Atsushi Sakai

Toshiyuki Hata

Masami Sawada

Yoshinori Kaya

Masayuki Ida

Satoru Tokuda

Mitsuru Yoshida

Masaki Kojima

Kazunori Doi

Ryuuji Umemoto

A semiconductor device includes: a first semiconductor chip including a first MOSFET of n-type and a first parasitic diode; and a second semiconductor chip including a second MOSFET of n-type and a second parasitic diode. A first source electrode and a first gate wiring are formed in a first front surface of the first semiconductor chip, and a first drain electrode is formed in a first back surface of the first semiconductor chip. A second source electrode and a second gate wiring are formed in a second front surface of the second semiconductor chip, and a second drain electrode is formed in a second back surface of the second semiconductor chip. The first front surface and the second front surface face each other such that the first source electrode and the second source electrode are in contact with each other via a conductive paste.

Semiconductor device and circuit device

To reduce on-resistance while suppressing a characteristic variation increase of a vertical MOSFET with a Super Junction structure, the vertical MOSFET includes a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions disposed in the n-type drift region at a lower portion of the p-type base region by a predetermined interval, a plurality of trenches whose bottom surface reaches a position deeper than the p-type base region and that is disposed between the adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches, and an n-type source region formed on the side of the gate electrode in the p-type base region.

Semiconductor device

In a trench gate type power MOSFET having a super-junction structure, both improvement of a breakdown voltage of a device and reduction of on-resistance are achieved. The trench gate and a column region are arranged so as to be substantially orthogonal to each other in a plan view, and a base region (channel forming region) and the column region are arranged separately in a cross-sectional view.

Semiconductor device and method of manufacturing the same

A semiconductor device according to an embodiment comprises: a cell portion in which a vertical type MOSFET is formed; and a termination portion arranged adjacent to the cell portion. The termination portion includes a connection trench gate provided along a first direction. The cell portion includes: a plurality of first column regions provided along a second direction intersecting the first direction; and a plurality of trench gates provided along the second direction such that two trench gates are arranged between the two adjacent first column regions. The plurality of trench gates extend from the cell portion to the termination portion and are connected to the connection trench gate. The plurality of first column regions extend from the cell portion to the termination portion, and the termination portion includes a plurality of second column regions different from the plurality of first column regions.

A semiconductor device for suppressing a variation in characteristics caused by a current flowing at the time of breakdown is disclosed. The first power MOS transistor Qand the column CLM are formed in the first element region FCM defined in the epitaxial layer NEL, and the second power MOS transistor Qis formed in the second element region RCM. The first power MOS transistor Qincludes a first trench gate electrode TGE, and the second power MOS transistor Qincludes a second trench gate electrode TGE. The depth GDPof the first trench gate electrode TGEis shallower than the depth GDPof the second trench gate electrode TGE

A semiconductor device which simplifies the manufacturing process while decreasing the width of separation between a first MOS transistor area and a second MOS transistor area, and a method for manufacturing the semiconductor device. A first MOS transistor and a second MOS transistor configure a bidirectional switch. The first MOS transistor and second MOS transistor each have a vertical trench structure. A first impurity region abuts on the side wall of a first gate trench of a first MOS transistor element outside the first MOS transistor area and is electrically coupled to a first source region.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a semiconductor substrate, a gate electrode, and a first contact plug. The semiconductor substrate includes a first surface and a second surface. Over the semiconductor substrate, a source region, a drain region, a drift region, and a body region are formed. A first trench in which the gate electrode is buried is formed in the first surface. The first surface includes an effective region and a peripheral region. The first trench extends from the peripheral region over the effective region along a first direction. The gate electrode includes a portion opposed to and insulated from the body region sandwiched between the source region and the drift region. In the peripheral region, the first contact plug is electrically coupled to the gate electrode buried in the first trench such that its longer side is along the first direction when seen in a plan view.

A semiconductor device and a circuit arrangement are provided so as to reduce an on resistance. A first power MOS transistor and a second power MOS transistor are formed on the same semiconductor substrate. A first power MOS transistor formed in a first element formation region has a columnless structure including no columns. The second power MOS transistor formed in a second element formation region has an SJ structure including columns.

Semiconductor device and circuit arrangement using the same

A semiconductor device according to one embodiment includes a semiconductor substrate having a main surface and a back surface opposite to the main surface, a drift region of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, and a gate electrode. The semiconductor substrate has a trench in the main surface. The gate electrode is formed in the trench. A distribution of an impurity concentration in the base region has a plurality of peak values along a direction of depth from the main surface toward the back surface, and the number of peak values is four or more.

The present invention is provided to easily manufacture an IPD as any of a high-side switch and a low-side switch. A level shifting circuit is coupled to an input terminal, a first terminal, and a grounding terminal. Drive power of the level shifting circuit is supplied from the first terminal. An output signal of the level shifting circuit is input to a driver circuit. The driver circuit is coupled to the first terminal and a second terminal. Drive power of the driver circuit is supplied from the first terminal. A transistor has a gate electrode coupled to the driver circuit, a source coupled to the second terminal, and a drain coupled to a third terminal.

In a high voltage MOS transistor, in a portion immediately below the gate electrode, peaks of concentration distribution in depth direction of a first conductivity type impurity and a second conductivity type impurity in the drain offset region are in the same depth, the second conductivity type impurity being higher concentrated than the first conductivity type impurity.

A power switch circuit includes an output transistor which is connected between a first power supply terminal and an output terminal, and drives a load, an abnormality detecting circuit which detects an abnormal state of the output transistor, a resistance element which generates a resistance component by a diffusion layer formed on a well region, and is provided between an input terminal and a control terminal of the output transistor, and a well potential switching circuit which switches a voltage to be supplied to the well region between a voltage of the output terminal and a voltage of a second power supply terminal based on a detection result by the abnormality detecting circuit.

Power switch circuit having variable resistor coupled between input terminal and output transistor and changing its resistance based on state of output transistor

A charge pump circuit is provided with a capacitor for generating a boosted voltage from a power supply voltage in response to a clock signal; and an output node from which the boosted voltage is externally outputted. The capacitor includes a first well formed within a substrate, a second well formed within the first well, first and second diffusion regions formed within the second well to receive the clock signal, a channel region provided between the first and second diffusion regions in which channel region a channel is formed in response to the clock signal; and an electrode positioned over the channel region across a dielectric and connected with the output node. The output node is also connected with the first well to apply said boosted voltage to the first well.

Charge pump circuit with reduced parasitic capacitance

In a dead time control circuit, a delay circuit is connected to an input terminal and adapted to delay signals therethrough by a delay time corresponding to a dead time. A logic circuit has a first input connected via the delay circuit to the input terminal, a second input connected directly to the input terminal, and an output connected to an output terminal. The dead time having adjustable temperature characteristics.

Dead time control circuit capable of adjusting temperature characteristics of dead time

A high withstand voltage diode for protecting a high-voltage transistor has a first region of a second conductivity type formed on the substrate of a first conductivity type, a high-concentration second region of the second type formed on the first region , a third region of the first conductivity type formed so as to, be adjacent to the first region , a high-concentration fourth region of the first conductivity type formed on the surface of the third region , and a gate electrode that straddles the first region and the third region with an intervening gate oxide film, and which is electrically connected to the fourth region.

Growing community of inventors

Ibaraki, Japan

Hiroshi Yanagigawa