Renesas Technology Corp.

Other

Renesas Electronics Corporation

Hiroshi Tobimatsu

Mahito Sawada

Hiroyuki Kawata

Yuuki Kamiura

Takuya Futase

Koyu Asai

Kouji Oda

Akio Nishida

Koji Shibata

Jun Shibata

Tsuyoshi Koga

Kouji Shibata

Kazuhito Matsukawa

Seiji Okura

Yoshiko Higashide

To provide a technology capable of improving reliability and manufacturing yield of a semiconductor device by reducing variations of electrical characteristics in connection hole portions. After a semiconductor wafer is placed over a wafer stage provided in a chamber for dry cleaning treatment of a deposition system, dry cleaning treatment is performed to a principal surface of the semiconductor wafer by supplying reducing gas, sequentially, heat treatment is performed to the semiconductor wafer at a first temperature of 100 to 150&#xb0; C. by a showerhead which is maintained at 180&#xb0; C. Next, after the semiconductor wafer is vacuum transferred from the chamber to a chamber for heat treatment, heat treatment is performed to the semiconductor wafer at a second temperature of 150 to 400&#xb0; C. in the chamber, thereby removing a product remaining over the principal surface of the semiconductor wafer.

Method of manufacturing semiconductor device

In a semiconductor chip A wherein an element layerhaving transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 &#x3bc;m or less, and thereafter, a gettering layeris formed on the back face of the semiconductor chip A. The gettering layeris formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.

Semiconductor chip having gettering layer, and method for manufacturing the same

An interconnection is provided with a dummy interconnection connected to an interconnection body, and the dummy interconnection is provided with a stress concentration portion in which tensile stress higher than that of the interconnection body is generated. In proximity to the stress concentration portion, an insulating film formed by high-density plasma CVD is provided, and the tensile stress is generated in the stress concentration portion by the insulating film. With this structure, the occurrence of a void can be prevented at any position in the interconnection body.

Interconnection structure of semiconductor device

An interconnection is formed on a semiconductor substrate having a semiconductor element formed thereon. Next, a passivation film is formed on the semiconductor substrate including the interconnection. Further, a polyimide film, which is served as a buffer coating film, is formed on the passivation film. Further, the polyimide film is patterned. Next, the passivation film is subject to etching while the patterned polyimide film is taken as a mask. Next, a hardened layer, which is formed on the surface of the polyimide film as a result of etching, is removed through ashing process. Next, the semiconductor substrate after ashing process is cured so as to transform the polyimide film into imide.

Method of manufacturing semiconductor device having passivation film and buffer coating film

A manufacturing method of a semiconductor device allowing successful filling of an insulating film by HDP-CVD (High Density Plasma-Chemical Vapor Deposition) in a gap or valley between densely placed interconnections is provided. The method includes the steps of forming semiconductor elements on a semiconductor substrate, forming on the semiconductor elements a plurality of interconnections with top protective layers side by side to electrically connect the semiconductor elements, forming a protective insulating film by CVD other than HDP-CVD to cover top and side surfaces of the interconnections and a bottom surface of a gap between the interconnections, and forming an insulating film by HDP-CVD to cover the protective insulating film and to fill in the gap between the interconnections covered with the protective insulating film.

Semiconductor device and manufacturing method thereof

A method of manufacturing a semiconductor device is provided, which prevents a polyimide film from coming unstuck from a film to be subjected to isotropic etching, and further prevents deposits adhered to respective side faces of the films from coming off, during a heat treatment for imidizing the polyimide film. Isotropic etching is performed on a silicon nitride film using, as a mask, a polyimide film having a predetermined pattern formed therein. Next, a heat treatment is carried out to imidize the polyimide film prior to performing anisotropic etching on a silicon oxide film . During the heat treatment for imidizing the polyimide film , since deposits, which are to be generated by anisotropic etching, are not yet adhered to the respective side faces of the films, the polyimide film does not come unstuck from the silicon nitride film . Further, the deposits which are adhered to the respective side face of the films after the heat treatment will not come off.

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Tokyo, Japan

Hiroshi Tobimatsu