Hitachi, Ltd.

Texas Instruments Corporation

Other

Hitachi Ltd, of Japan

Hiroshi Otori

Takesada Akiba

Goro Kitsukawa

William R McKee

Jeffrey E Koelling

Troy H Herndon

Masayuki Nakamura

Kazuhiko Kajigaya

Hiroki Fujisawa

Seiji Narui

Masanori Isoda

Akira Ohta

Adin E Hyslop

Minoru Ebihara

Takayuki Kawahara

Hugh Pryor McAdams

Kazuyoshi Oshima

Kazuyuki Miyazawa

Masaharu Kubo

Tsugio Takahashi

Masayuki M Nakamura

Wah Kit Loh

Masatoshi Hasegawa

Atsuyoshi Koike

Tetsuro Matsumoto

Mitsugu Kusunoki

Fumiyuki Kanai

Masatoshi Sakamoto

Hideo Sunami

A semiconductor memory device that satisfies needs of both a large number of memory banks and a higher operation speed is provided. A semiconductor memory device includes a plurality of data terminal pads, and a plurality of memory banks independently subject to memory access. Each of the memory banks is divided into a plurality of submemory banks. The data terminal pads are also divided into a plurality of groups so as to be associated with submemory banks obtained by the division. Blocks each including submemory banks obtained by the division and data terminal pads associated with the submemory banks are arranged so as not to overlap each other on a semiconductor chip.

Semiconductor memory device and semiconductor device

A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

System with meshed power and signal buses on cell array

Relief units (UNITb) each having electrically programmable electric fuses for storing information according to the difference in threshold voltage, and an address comparator are disposed in a second area, and relief units (UNITa) each having laser fuses and an address comparator are disposed in a first area. Both areas are adjacent to each other along an address signal wiring for each comparator, and the address signal wiring is laid out linearly. Even if the electric fuses and the laser fuses are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.

Semiconductor memory including a circuit for selecting redundant memory cells

Semiconductor device

An apparatus and method for a logic circuit that advantageously adapts to different operating voltages. In a preferred embodiment, a logic circuit of the present invention is implemented to drive a large capacitive load and includes a first driver, comprising a set of small, low-current drive transistors, a second driver, comprising a set of large, high-speed transistors, and an additional transistor connected between the two drivers. The additional transistor can be selectively enabled to speed up the operation of the logic circuit, and disabled to reduce the peak current of the logic circuit. The additional transistor is enabled by a voltage detection signal, which is active when the operating voltage of the chip is at a low level and inactive when the operating voltage of the chip is at a high level.

Sense amplifier driver having variable power-supply voltage

Growing community of inventors

Ome, Japan

Hiroshi Otori