Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Fujitsu Corporation

Hiroshi Morioka

Masanori Terahara

Jusuke Ogura

Sergey Pidin

Toru Anezaki

Kenichi Goto

Kenichi Okabe

Shigeo Satoh

Sadahiro Kishii

Junichi Ariyoshi

Masaki Okuno

Kaina Suzuki

Manabu Kojima

Rintaro Suzuki

A semiconductor device having a contact structure is provided. The semiconductor device includes: a conductive region; a first film and a second film which are formed over the conductive region to realize a layer; and a contact electrode which extends through the layer to the conductive region, and is formed so as to replace a portion of the layer with a portion of the contact electrode, where the portion of the layer is constituted by only the first film, only the second film, or both of a portion of the first film and a portion of the second film, and the portion of the first film occupies a major part of the portion of the layer.

Semiconductor device and process for producing the same

A method of manufacturing a semiconductor device has forming a first conductive film over a semiconductor substrate, etching the first conductive film, forming a plurality of first conductive patterns arranged in a first direction, and forming a side surface on an outside of a conductive pattern positioned at an end among the plurality of first conductive patterns such that the side surface has a first inclination angle smaller than a second inclination angle of a side surface on an inside of the conductive pattern positioned at the end, forming a first insulation film over the plurality of first conductive patterns, and forming a second conductive pattern over the first insulation film.

Semiconductor device and method of manufacturing thereof

A method for forming a pattern includes the steps of: (a) preparing a lower hard mask layer and an upper hard mask layer stacked on an etching target film; (b) forming a resist pattern above the upper hard mask layer; (c) etching the upper hard mask film by using the resist pattern as an etching mask to form an upper hard mask; (d) after the step (c), removing the resist pattern; (e) after the step (d), thinning the upper hard mask by etching; (f) etching the lower hard mask film by using the thinned upper hard mask as an etching mask to form a lower hard mask; and (g) etching the etching target film by using the upper hard mask and the lower hard mask as an etching mask. The method for forming a pattern can etch a fine pattern with good yield.

Method for manufacturing micro structure

Photosensitive resist material is coated on a substrate and exposed and developed to form a resist pattern. The surface layer of sidewalls and a top wall of the resist pattern is etched by plasma of a mixture gas of a first gas and an SOgas, the first gas being at least one gas selected from a group consisting of He, Ne, Ar, Xe, Kr, CO, COand N. Resist pattern deformation and pattern collapse can be prevented while the resist pattern shrinks.

Micro pattern forming method and semiconductor device manufacturing method

The method for fabricating a semiconductor device comprises the steps of: forming on a silicon substratea hard maskof a silicon oxide film, and a silicon nitride filmhaving a width smaller than a width of the silicon oxide film; etching the silicon substratewith the hard maskas the mask to form a trenchfor defining an active regionin the silicon substrate; and forming a silicon oxide filmon the silicon substratewith the trenchformed in.

Method for fabricating semiconductor device

A method of fabricating a semiconductor device includes a dry etching process of a silicon surface. The dry etching process is conducted by an etching gas containing at least one gas species selected from the group consisting of: HBr, HCl, Cl, Brand HI, wherein the dry etching process includes a first step conducted at a first temperature; and a second step conducted at a second temperature.

Semiconductor device and fabrication process thereof

A semiconductor device is disclosed that includes a semiconductor substrate, a device region disposed at a predetermined location of the semiconductor substrate, and a shallow trench isolation region that isolates the device region. The shallow trench isolation region includes a trench, a nitride film liner disposed at an upper portion of a side wall of the trench, and a thermal oxide film disposed at a lower portion of the side wall of the trench. The shallow trench isolation is arranged such that the width of a second portion of the shallow trench isolation region at which the thermal oxide film is disposed may be wider than the width of a first portion of the shallow trench isolation region at which the lower end of the nitride film liner is disposed.

Semiconductor device and method for manufacturing the same

The semiconductor device fabrication method comprises the step of forming a first insulation filmover a semiconductor substratethe step of forming a semiconductor filmover the first insulation filmthe step of forming a resist filmover the semiconductor filmthe step of forming openingsin the resist filmthe step of etching the semiconductor filmwith the resist filmas the mask; the step of etching the first insulation filmwith the semiconductor filmas the mask; and the step of etching the semiconductor substratewith the first insulation filmas the mask to form trenchesin the semiconductor substrateSilicon nitride film is patterned, using a mask of polysilicon film, whereby the silicon nitride film can be etched with high selectivity to the polysilicon film. Accordingly, a good pattern of the silicon nitride film can be formed. Even when micronized trenches are formed in a semiconductor substrate with silicon nitride film as a mask, the trenches can be formed in a required configuration. Thus, good element isolation regions can be formed, further micronized.

Semiconductor device fabrication method

A method of manufacturing a CMOS semiconductor device able to reduce the effective thickness of the gate insulating film and able to secure stable performance is provided. The method in one embodiment comprises the steps of: forming a polycrystalline silicon film on a gate insulating film; introducing an n-type impurity into the polycrystalline silicon film in an nMOS formation region before gate processing of the polycrystalline silicon film; performing heat treatment so that the impurity diffuses in the polycrystalline silicon film and is activated; and patterning the polycrystalline silicon to form a gate pattern before introducing an impurity into the polycrystalline silicon film at a pMOS formation region.

Growing community of inventors

Kawasaki, Japan

Hiroshi Morioka