Mitsubishi Denki Kabushiki Kaisha

Other

Ryoden Semiconductor System Engineering Corporation

Panasonic Corporation

Hiroshi Matsuo

Yuichi Yokoyama

Shinya Inoue

Yuji Yamamoto

Takuji Oda

Kiyoshi Maeda

Takaaki Murakami

Kaoru Motonami

Shigeru Shiratake

Yasuyoshi Itoh

Kenji Yasumura

Satoshi Hamamoto

Ritsuko Gotoda

Kenji Morisawa

Shinya Watanabe

Toshihiro Keishima

Miyuki Kani

An induction heater which has an electrical conductor between a heating coil and a top plate. The electrical conductor has an extended portion formed downward from its outer periphery. The extended portion has a connector at its tip for coupling to a low-potential part. A thermal-connection reducing means is provided on the extended portion. A cross-sectional shape near a bent portion of the extended portion is made uniform. With the above structure, the electrical conductor has both the functions of decreasing the buoyancy and electrostatic shielding. This structure uses a smaller number of components, eliminates the risk of electric shock to the human body, and prevents uplift of an object to be heated. The thermal-connection reducing means reduces heat conduction to a connected part. Accordingly, a highly reliable and compact apparatus becomes available.

Induction heater

An improved etching method allowing the formation of a silicon nitride film with an adequate film thickness at the sidewall portion of a pattern is disclosed. A silicon nitride film formed to cover a stepped pattern is dry-etched, employing plasma of mixed gases containing CH F and O . As a result, a sidewall spacer of the silicon nitride film is formed at the sidewall of the pattern in a self-aligned manner.

Method of manufacturing semiconductor device

A hard mask insulating layer is formed on a gate electrode which is formed on a main surface of a silicon substrate with a gate insulating layer interposed. An SiN sidewall spacer is directly formed on a thin SiO layer which is formed to cover a side surface of the gate electrode. A contact hole is formed to penetrate an interlayer insulating layer formed on an SiN stopper layer and reach the main surface of the silicon substrate.

Method of fabricating a semiconductor device

A hard mask insulating layer is formed on a gate electrode which is formed on a main surface of a silicon substrate with a gate insulating layer interposed. An SiN sidewall spacer is directly formed on a thin SiO,layer which is formed to cover a side surface of the gate electrode. A contact hole is formed to penetrate an interlayer insulating layer formed on an SiN stopper layer and reach the main surface of the silicon substrate.

Semiconductor device and fabrication method thereof

There are provided a semiconductor device, which includes an element isolating oxide film having a good upper flatness, and a method of manufacturing the same. Assuming that t.sub.G represents a thickness of a gate electrode layer 6, a height t.sub.U to an upper surface of a thickest portion of element isolating oxide film 4 from an upper surface of a gate insulating film 5 and an acute angle .theta.i defined between the upper surfaces of element isolating oxide film 4 and gate insulating film are set within ranges expressed by the formula of {.theta.i, t.sub.U .linevert split.0.ltoreq..theta.i.ltoreq.56.6.degree., 0.ltoreq.t.sub.U .ltoreq.0.82t.sub.G }. Thereby, an unetched portion does not remain at an etching step for patterning the gate electrode layer to be formed later. This prevents short-circuit of the gate electrode. Since the element isolating oxide film has the improved flatness, a quantity of overetching in an active region can be reduced at a step of patterning the gate electrode. This prevents shaving of the gate insulating film and the underlying substrate surface.

Semiconductor device having an element isolating oxide film and method

An improved etching method allowing the formation of a silicon nitride film with an adequate film thickness at the sidewall portion of a pattern is disclosed. A silicon nitride film formed to cover a stepped pattern is dry-etched, employing plasma of mixed gases containing CH.sub.2 F.sub.2 and O.sub.2. As a result, a sidewall spacer of the silicon nitride film is formed at the sidewall of the pattern in a self-aligned manner.

An improved semiconductor memory device in which an electric circuit operates normally is provided. A block of memory cells of a dynamic random access memory is provided on a semiconductor substrate. A dummy storage node is provided near a corner portion of the memory cell block. A dummy cell plate is provided such that it covers the dummy storage node and is electrically insulated from a main cell plate of the DRAM.

Growing community of inventors

Hyogo, Japan

Hiroshi Matsuo