Kabushiki Kaisha Toshiba

Fujitsu Corporation

Sony Corporation

Sanbio, Inc.

Toshiba Memory Corporation

Toshiba Kikai Kabushiki Kaisha

Kioxia Corporation

Toagosei Company, Ltd.

Sandisk Corporation

Cellfree Sciences Co., Ltd.

Hiroshi Kanno

Takayuki Tsukamoto

Yoichi Minemura

Takamasa Okawa

Atsushi Yoshida

Takafumi Shimotori

Kenichi Murooka

Mari Dezawa

Hajime Sawada

Masahiko Takano

Hideyuki Tabata

Reika Ichihara

Hiroaki Yada

Noriyuki Harada

Tomonori Kurosawa

Mizuki Kaneko

Mitsuru Sato

Takashi Ishida

Hirofumi Inoue

Takahiko Sasaki

Shigeru Fujita

Tatsuo Hayashi

Hiroshi Ito

Jun Nishimura

Natsuki Kikuchi

Kenji Satoh

Yuuichi Abe

Masahiro Une

Yoshiaki Fukuzumi

Tetsuhiko Yoshida

Nobuhiro Hayashi

Takahiro Sugimoto

Nobuaki Yasutake

Hiroyuki Fukumizu

Nahoko Kobayashi

Fumitoshi Ito

Tatsufumi Hamada

Kunio Watanabe

Tatsuya Okamoto

Toshiya Miyazaki

Jun Hirota

Kouichirou Kasama

Ken Komiya

Shinya Naito

Satoshi Konagai

Makoto Toyoshima

Minoru Maruyama

Masanori Komura

Masao Hirosawa

Shuuji Fujiwara

Takeo Oshiro

Takashi Kamiyama

Koichi Ozawa

Tomofumi Zushi

Yukio Takanashi

Koichi Kanazawa

Takashi Goto

Tatsuo Ishida

Eiji Miyazaki

Hironobu Hamanaka

Tsugio Toyama

Naoki Yamamoto

Yasuyuki Ono

Youichi Minemura

Hidekazu Nakamura

The semiconductor storage device of an embodiment includes a first conductive layer, a stack disposed above the first conductive layer and including a plurality of second conductive layers in a first direction, and a columnar body that extends in the first direction through the stack, and includes a semiconductor layer and a charge storage film provided between the plurality of conductive layers and the semiconductor layer. A first conductive layer out of the plurality of conductive layers is connected to the semiconductor layer, and the semiconductor layer includes a first region in which a concentration of an n-type impurity is higher than a concentration of a p-type impurity, a second region in which a concentration of a p-type impurity is higher than a concentration of an n-type impurity, and a third region contacted to the first conductive layer and disposed closer to the first region than the second region in the first direction.

Semiconductor storage device

A semiconductor storage device includes a plurality of memory cell transistors, a first wiring electrically connected to the plurality of memory cell transistors, and an erasing circuitry. The erasing circuitry is configured to erase data stored in the memory cell transistors by applying a first voltage to the first wiring, and apply the first voltage such that the first voltage rises to a first value, then falls from the first value to a second value, and is then maintained at the second value.

Semiconductor storage device having voltage erasing operation capability and control method thereof

There is provided a method of inducing differentiation of bone marrow stromal cells to neural cells or skeletal muscle cells by introduction of a Notch gene. Specifically, the invention provides a method of inducing differentiation of bone marrow stromal cells to neural cells or skeletal muscle cells in vitro, which method comprises introducing a Notch gene and/or a Notch signaling related gene into the cells, wherein the finally obtained differentiated cells are the result of cell division of the bone marrow stromal cells into which the Notch gene and/or Notch signaling related gene have been introduced. The invention also provides a method of inducing further differentiation of the differentiation-induced neural cells to dopaminergic neurons or acetylcholinergic neurons. The invention yet further provides a treatment method for neurodegenerative and skeletal muscle degenerative diseases which employs neural precursor cells, neural cells or skeletal muscle cells produced by the method of the invention.

Neural precursor cells expressing exogenous Notch intracellular domain

A semiconductor memory device includes a substrate, gate electrodes arranged in a thickness direction of the substrate, first and second semiconductor layers, a gate insulating film, and a first contact. The first semiconductor layer extends in the thickness direction and faces the gate electrodes. The gate insulating film is between the gate electrodes and the first semiconductor layer. The second semiconductor layer is between the substrate and the gate electrodes and connected to a side surface of the first semiconductor layer in a surface direction. The first contact extends in the thickness direction and electrically connected to the second semiconductor layer. The second semiconductor layer includes a first region in contact with the side surface of the first semiconductor layer and containing P-type impurities, and a first contact region electrically connected to the first contact and having a higher concentration of N-type impurities than the first region.

Semiconductor memory device

A semiconductor device includes a first semiconductor layer that is an electrically-conductive polycrystalline semiconductor layer and a second semiconductor layer on the first semiconductor layer. The second semiconductor layer is an electrically-conductive polycrystalline semiconductor layer having a smaller average grain size than the first semiconductor layer. A plurality of electrode layers are stacked on the second semiconductor layer at intervals in a first direction. A third semiconductor layer extends in the first direction through the first semiconductor layer, the second semiconductor layer, and each of the electrode layers and contacts the second semiconductor layer. A charge storage layer is between the plurality of electrode layers and the third semiconductor layer.

Semiconductor device and method for manufacturing the same

A semiconductor memory device according to an embodiment includes a base portion, a laminated body, a second conductive layer, and a columnar body. The columnar body includes a semiconductor body and a charge storage film. The semiconductor body includes a first region and a second region. The first region extends from a connection portion between the semiconductor body and the first semiconductor portion to the inside of the second conductive layer. The first region includes a first material. The second region is positioned closer to the laminated body than the first region is and is configured such that at least a portion is present within the second conductive layer. The second region does not include the first material or has a concentration of the first material which is lower than that in the first region. A first outer circumferential length of the semiconductor body within the second conductive layer is larger than a second outer circumferential length of the semiconductor body on a first surface which is an interface between the second conductive layer and the laminated body.

Treatment of CNS disorders using descendants of MSCS expressing an exogenous Notch intracellular domain

According to one embodiment, a semiconductor memory device includes a base semiconductor layer, first and second conductive layers, a semiconductor body, a memory layer, first and second semiconductor regions, and an insulating portion. The first conductive layer is separated from the base semiconductor layer in a first direction. The second conductive layer is provided between the base semiconductor layer and the first conductive layer. The semiconductor body extends through the first conductive layer in the first direction. The memory layer is provided between the semiconductor body and the first conductive layer. The first semiconductor region is provided between the memory layer and the base semiconductor layer and between the semiconductor body and the base semiconductor layer, and is of a first conductivity type. The second semiconductor region is provided between the first semiconductor region and the memory layer, and is of a second conductivity type.

A semiconductor memory device includes a conductive layer on a source side; a first electrode layer provided on the conductive layer; a second electrode layer provided between the conductive layer and the first electrode layer; a semiconductor layer extending through the first electrode in a first direction from the conductive layer to the first electrode layer; a first semiconductor body provided between the conductive layer and the semiconductor layer, the first semiconductor body including first impurities; and a second semiconductor body provided between the conductive layer and the first semiconductor body, the second semiconductor body including second impurities with a higher concentration than a concentration of the first impurities in the first semiconductor body. A diffusion coefficient of the second impurities in the second semiconductor body is smaller than a diffusion coefficient of the second impurities in the first semiconductor body.

A semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes: a plurality of first conductive layers that are stacked; a memory layer provided on a side surface of the plurality of the first conductive layers; and a second conductive layer that contacts the side surface of the plurality of the first conductive layers via the memory layer. A thickness of the first conductive layer disposed at the first position is larger than a thickness of the first conductive layer disposed at the second position. The control circuit is configured to apply a first voltage to a selected first conductive layer. The control circuit changes a value of the first voltage based on a position of the selected first conductive layer.

Three-dimensional resistive memory device with adjustable voltage biasing

Treatment of CNS disorders using descendants of MSCs expressing an exogenous Notch intracellular domain

A semiconductor memory device according to an embodiment described below comprises: first lines arranged in a first direction perpendicular to a main surface of a substrate and extending in a second direction crossing the first direction; second lines arranged in the second direction, extending in the first direction, and intersecting the first lines; memory cells disposed at intersections of the first lines and the second lines; and an interlayer insulating film provided between the second lines. The interlayer insulating film has an air gap extending continuously in the first direction so as to intersect at least some of the first lines aligned along the first direction. The interlayer insulating film also includes an insulating film positioned above the air gap and having a curved surface that protrudes toward a direction of the substrate.

This semiconductor memory device comprises a memory cell array that includes: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; a plurality of memory cells each disposed at an intersection of the plurality of first lines and the plurality of second lines and including a variable resistance element; and a select transistor respectively connected to an end of the plurality of first lines. The select transistor includes a gate electrode, a gate insulating film, and a conductive layer. Moreover, one end of that conductive layer is connected to the end of the first line, and a non-linear resistance layer configured from a non-linear material is connected between the first line and the conductive layer.

Growing community of inventors

Yokkaichi, Japan

Hiroshi Kanno