Headway Technologies, Incorporated

Sae Magnetics (h.k.) Limited

Tdk Corporation

Hiroshi Ikejima

Yoshitaka Sasaki

Hiroyuki Ito

Atsushi Iijima

Tatsuya Harada

Nobuyuki Okuzawa

Satoru Sueki

A layered chip package includes a main body and wiring. The main body has a main part. The main part has a top surface and a bottom surface and includes a plurality of layer portions that are stacked. The wiring includes a plurality of lines passing through all the plurality of layer portions. Each layer portion includes a semiconductor chip and a plurality of electrodes. The semiconductor chip has a first surface, and a second surface opposite thereto. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. The plurality of layer portions include two or more pairs of first and second layer portions in each of which the first and second layer portions are arranged so that the first or second surfaces of the respective semiconductor chips face each other. The plurality of electrodes include a plurality of first connection parts and a plurality of second connection parts. In the first layer portion, the plurality of first connection parts are in contact with the plurality of lines. In the second layer portion, the plurality of second connection parts are in contact with the plurality of lines.

Layered chip package and method of manufacturing same

A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of stacked layer portions. A method of manufacturing the layered chip package includes the step of fabricating a layered substructure and the step of cutting the layered substructure. The layered substructure includes: a plurality of arrayed pre-separation main bodies; a plurality of accommodation parts disposed between two adjacent pre-separation main bodies; and a plurality of preliminary wires accommodated in the accommodation parts. The accommodation parts are formed in a photosensitive resin layer by photolithography. In the step of cutting the layered substructure, the plurality of pre-separation main bodies are separated from each other, and the wires are formed by the preliminary wires.

Method of manufacturing layered chip package

A layered chip package includes a main body. The main body includes a main part, and further includes first terminals and second terminals disposed on the top and bottom surfaces of the main part, respectively. The main part includes first and second layer portions, and through electrodes penetrating them. The through electrodes are electrically connected to the first and second terminals. Each of the layer portions includes a semiconductor chip having a first surface and a second surface opposite thereto, and further includes surface electrodes. The surface electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the surface electrodes of the first layer portion. The second terminals are formed by using the surface electrodes of the second layer portion.

A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. Each layer portion includes a semiconductor chip having a first surface and a second surface opposite thereto, and includes a plurality of electrodes. The electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the electrodes of the first layer portion, and the second terminals are formed by using the electrodes of the second layer portion.

A method of manufacturing a layered chip package that includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of layer portions. The method includes fabricating a plurality of substructures, and completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body. Each substructure is fabricated through the steps of: fabricating a pre-substructure wafer including a plurality of pre-semiconductor-chip portions aligned; distinguishing between a normally functioning pre-semiconductor-chip portion and a malfunctioning pre-semiconductor-chip portion among the plurality of pre-semiconductor-chip portions included in the pre-substructure wafer; and forming electrodes connected to the normally functioning pre-semiconductor-chip portion and having respective end faces located in the side surface of the main body on which the wiring is disposed, without forming any electrode connected to the malfunctioning pre-semiconductor-chip portion.

A layered chip package includes a plurality of layer portions that are stacked, each of the layer portions including a semiconductor chip. The plurality of layer portions include at least one first-type layer portion and at least one second-type layer portion. The semiconductor chip has a circuit, a plurality of electrode pads electrically connected to the circuit, and a plurality of through electrodes. In every vertically adjacent two of the layer portions, the plurality of through electrodes of the semiconductor chip of one of the two layer portions are electrically connected to the respective corresponding through electrodes of the semiconductor chip of the other of the two layer portions. The first-type layer portion includes a plurality of wires for electrically connecting the plurality of through electrodes to the respective corresponding electrode pads, whereas the second-type layer portion does not include the wires.

Layered chip package

In a ceramic capacitor according to the present invention, an interdiginated pair of internal electrodes are arranged, on a substrate, perpendicular to a surface of the substrate, and a ceramic dielectric member is filled into a gap between this pair of internal electrodes. For this reason, the dimensions of the internal electrodes do not substantially change before and/or after the formation of the ceramic dielectric member, whereby the dimensions formed at the time of internal electrode can be maintained. According to this ceramic capacitor, since the internal electrode dimensions can be easily controlled like this, dimensional control of internal electrode spacing can also be easily carried out.

Ceramic capacitor and method of manufacturing same

A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. The first and second terminals are formed by using electrodes of the first and second layer portions. The layered chip package is manufactured by fabricating a layered substructure by stacking two substructures each of which includes an array of a plurality of preliminary layer portions, and then cutting the layered substructure. The layered substructure includes a plurality of preliminary wires that are disposed between two adjacent pre-separation main bodies and are to become the plurality of wires.

In a ceramic capacitor according to the present invention, the electrode strips of an internal electrode and the dielectric strips of a ceramic dielectric member are arranged perpendicularly to the surface of a substrate, and as such, the plurality of electrode strips and the plurality of dielectric strips are arranged alternately along a parallel direction relative to the substrate surface. That is, the electrode strips and the dielectric strips are multi-layered along a parallel direction relative to the substrate surface, thereby facilitating the realization of multi-layering in the ceramic capacitor by a known patterning technology.

A composite layered chip package includes a plurality of subpackages stacked on each other. Each subpackage includes a main body and wiring. The main body includes a main part including a plurality of layer portions, and further includes first terminals and second terminals that are disposed on top and bottom surfaces of the main part, respectively. The wiring is electrically connected to the first and second terminals. The number of the plurality of layer portions included in the main part is the same for all the plurality of subpackages, and the plurality of layer portions in every subpackage include at least one first-type layer portion. In each of at least two of the subpackages, the plurality of layer portions further include at least one second-type layer portion. The first-type layer portion includes a semiconductor chip connected to the wiring, whereas the second-type layer portion includes a semiconductor chip not connected to the wiring.

Composite layered chip package

A layered chip package includes a main body, and wiring disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions stacked; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. The plurality of layer portions include a first-type layer portion and a second-type layer portion. The first-type layer portion includes a conforming semiconductor chip, and a plurality of first-type electrodes that are connected to the semiconductor chip and the wiring. The second-type layer portion includes a defective semiconductor chip, and a plurality of second-type electrodes that are connected to the wiring and not to the semiconductor chip.

A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. Each layer portion includes a semiconductor chip. The plurality of second terminals are positioned to overlap the plurality of first terminals as viewed in a direction perpendicular to the top surface of the main body. A plurality of pairs of first and second terminals that are electrically connected via the wires include a plurality of pairs of a first terminal and a second terminal that are positioned not to overlap each other.

A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

A layered chip package includes a main body and wiring. The main body includes a main part including a plurality of stacked layer portions, and a plurality of terminals disposed on the top and bottom surfaces of the main part. The wiring includes a plurality of lines electrically connected to the plurality of terminals. The plurality of lines include a plurality of common lines and a plurality of layer-dependent lines. Each of the plurality of layer portions includes: a plurality of common electrodes electrically connected to the plurality of common lines; a plurality of non-contact electrodes that are electrically connected to the layer-dependent lines and are not in contact with the semiconductor chip in the layer portion; and a selective connection electrode selectively electrically connected to only the layer-dependent line that the layer portion uses among the plurality of layer-dependent lines. The layer-dependent lines are greater than the common lines in maximum width.

A layered chip package has a main body including pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The pairs of layer portions include specific pairs of layer portions. Each of the specific pairs of layer portions includes a first-type layer portion and a second-type layer portion. The first-type layer portion includes electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes. The specific pairs of layer portions are provided in an even number.

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Hong Kong, China

Hiroshi Ikejima