System Jd Co., Ltd.

Japan Science and Technology Agency

Kyushu Institute of Technology

Semiconductor Technology Academic Research Center

Hiroshi Date

Seiji Kajihara

Kohei Miyase

Yoshihiro Minamoto

Xiaoqing Wen

Hiroyuki Yamashita

Toshinori Hosokawa

Michiaki Muraoka

Toshiyuki Shigemura

Shigenori Matsuo

Xiaqing Wen

A fault diagnosis method utilizing a fault diagnosis system for diagnosing a photovoltaic module by estimating a fault location, the fault diagnosis system including a signal generator for generating and inputting an input signal into a positive terminal or a negative terminal of the photovoltaic module, a waveform observer for observing a reflected output signal from an open end or the fault location, a diagnosis unit for estimating the fault location based on the output signal, a conductive body, and an alignment unit for controlling the positions of the conductive body and/or the photovoltaic module. The diagnosis method includes controlling the positions of the conductive body and/or the photovoltaic module, observing the output signal of the input signal, and estimating the fault location based on two reflected output signals of input signals inputted into the positive terminal and the negative terminal of the photovoltaic module.

Fault diagnosis system, fault diagnosis device, fault diagnosis method, program, computer-readable medium, and device under test

Provided are a conversion device and the like for converting a initial test pattern given in advance into a test pattern of a bit constitution of different logic values, without losing the fault coverage of transition delay fault which can be detected by the constitution element of the initial test pattern. The conversion device converts an initial test patterngiven in advance for a logic circuit into an intermediate test patternof a bit constitution of different logic values, where the constitution elements of the initial test patternare at least two test vectors applied in succession. The conversion device includes a decision means for deciding a combination of logic values in the initial test patternwhich meet a detection condition of faults of the logic circuit which can be detected by applying the constitution elements.

Conversion device, conversion method, program, and recording medium

Provided are a generation device and the like for generating a test vector which can reduce capture power efficiently. The generation devicegenerates a test vector for a logic circuit by assigning logic values to each of a plurality of unspecified bits (X-bits) included in a test cube. The generation deviceincludes a selection unitfor selecting, among the plurality of X-bits, a target X-bit, which is a target of assigning a logic value, a capture transition metric calculation unitfor calculating capture transition metric caused by a test cube including an X-bit, and a logic value assignment unitfor assigning, to the selected target X-bit, a logic value which causes the smaller capture transition metric, by applying the capture transition metric calculation means to a first test cube obtained by assigning a logic value 0 to the selected target X-bit and to a second test cube obtained by assigning a logic value 1 to the selected target X-bit, and by comparing a capture transition metric caused by a first test cube and a capture transition metric caused by a second test cube.

Generating device, generating method, program and recording medium

Provided are a conversion device and others for converting a test vector set so as to reduce a logic value difference generated before and after scan capture in outputs of scan cells included in a full scan sequential circuit. A conversion device converts a test vector set corresponding to the full scan sequential circuit. The conversion device comprises a setting unit for setting a candidate bit which can be a don't care bit and a fixed bit which cannot be the don't care bit according to predetermined constraint conditions based on an input-output relationship in the logic circuit in order to identify the don't care bit identifiable as don't care from each test vector of the test vector set, and a logic value deciding unit for deciding a logic value for the don't care bit in view of a relationship in a plurality of bit pairs in relation to a test cube including the don't care bit identified by the setting unit.

A generation apparatus and the like for generating a test vector set capable of reducing differences in a logic value generated before and after a scan capture for outputs from scan cells included in a full-scan sequential circuit are provided. A generation apparatusgenerating an initial test vector setfor a logic circuit includes a target vector identification unitidentifying a test vector satisfying a predetermined criterion and to be selected for the number of bits (the number of bit transitions) whose logic values differ before and after scan capture with respect to outputs from scan cells included in the sequential circuit, from among test vectors in the initial test vector set, and a test vector set conversion unitconverting the test vector identified by the test vector identification unitand to be selected so as to reduce the number of bit transitions with respect to outputs from the scan cells included in the sequential circuit.

Provided are a diagnostic device and the like providing a favorable diagnosis result by further improving the diagnosis resolution. A diagnostic devicehas a symbol injection part, which is composed of a symbol injection part for an active elementand a symbol injection part for a passive element, an occurrence probability providing part, an equal occurrence probability providing part, and a switching part. A per-test X-fault diagnosis flow by the diagnostic deviceconsists of a stage for collecting diagnostic information and a stage for drawing diagnostic conclusion. The layout of a deep-submicron LSI circuit usually needs to involve multiple layers, which means that vias are extensively used. Since via information is utilized by the symbol injection part for a passive element, it becomes possible to locate defects to the via level, greatly improving the diagnostic resolution. Since, by the occurrence probability providing part, a new diagnosis value is used and, the occurrence probabilities of possible faulty logic combinations are taken into consideration, the reality in a deep-submicron LSI circuit is better reflected, which contributes to the improvement of diagnostic resolution.

Diagnostic device, diagnostic method, program, and recording medium

The area of the circuit to be added for easy testability is reduced. Operations contained in a behavioral description are extracted in an operation analyzing unit; when expanding any operation at the time of behavioral synthesis, if the area of the circuit can be reduced to a greater extent when a DFT is applied to the operation before expansion, a parameter indicating that the operation is not to be expanded at the time of behavioral synthesis is generated and DFT information is added to a DFT library. A behavioral synthesis unit, in accordance with the parameter, generates an RTL description without expanding the operation. A DFT unit implements the DFT by referring to the DFT library, and thereafter expands the operation.

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Fukuoka, Japan

Hiroshi Date