Hitachi, Ltd.

Other

Semiconductor Technology Academic Research Center

Hiroo Masuda

Katsuhiro Shimohigashi

Hiroshi Kawamoto

Kunihiko Ikuzaki

Hideo Miura

Jun Murata

Noriaki Okamoto

Makoto Ogasawara

Hiroyuki Ohta

Takahide Ikeda

Asao Nishimura

Takashi Hashimoto

Ryoichi Hori

Yoshiaki Kamigaki

Osamu Minato

Hideo Sunami

Yoichi Tamaki

Eiji Takeda

Masaharu Kubo

Yoshio Sakai

Jun Etoh

Isao Yoshida

Toshiaki Masuhara

Toru Kaga

Nobuyoshi Natsuaki

Yoshimune Hagiwara

Takeshi Kimura

Kazushige Sato

Shinichiro Mitani

Takaaki Hagiwara

Masaaki Nakai

Shinji Sakata

Kazuyoshi Hara

Yasunobu Tanizaki

Eiji Wakimoto

Katsumi Tsuneno

Kimiko Aoyama

Hisako Sato

Takahide Nakamura

A technique for a semiconductor device is provided that includes forming circuit regions on a device formation region and device isolation regions on a semiconductor substrate, a ratio of the width of a device isolation region to the width of adjacent circuit regions thereto is set at 2 to 50. A design method is also provided and includes conducting measurements such as of thicknesses of a pad oxide film and a nitride film, the internal stress of the nitride film, the width of both device formation and isolation regions, the depth of the etched portion of the nitride film for forming the groove in a device isolation region, conducting stress analysis in the proximity of the groove due to thermal oxidation, and setting values pertaining to the width of the device formation region and of the device isolation region which do not lead to occurrence of dislocation.

Method of designing a semiconductor device

There is provided a semiconductor device comprising a gate electrode which is formed on a semiconductor substrate through a gate insulating film and in which a plurality hexagonal rings are mutually connected so as to form a honeycomb structure, drain diffusion layers each formed in the semiconductor substrate on the inside of one hexagonal ring, source diffusion layers formed in the semiconductor substrate on the inside of a plurality of hexagonal rings which are adjacent to the hexagonal ring having the drain diffusion layer formed therein, and, insulating layers formed between respective source diffusion layers in the semiconductor substrate.

FET having a gate electrode of a honeycomb structure

A method is provided of fabricating a semiconductor device that includes forming a silicon oxide film on a semiconductor substrate. A silicon nitrite film may be formed on the silicon oxide film. A portion of the silicon nitrite film and the silicon oxide film may be removed at a desired portion. Additionally, a groove may be formed in the semiconductor substrate in the portion in which the silicon oxide film is removed. A part of the silicon oxide film may be etched back around the groove with hydrofluoric acid type at the portion in which the silicon nitrite film is located above. Additionally, an oxidized film may be formed in the groove of the semiconductor substrate and the groove may be oxidized.

Method of fabricating low stress semiconductor devices with thermal oxide isolation

Semiconductor device and method of fabricating same

A width of a circuit device isolation region and a width of a device region formed on a semiconductor substrate are determined in such a manner as to satisfy a condition which prevents the occurrence of dislocation due to thermal oxidation for forming the isolation region. In accordance with the manufacturing scheme, a semiconductor device produced includes a semiconductor substrate, a plurality of circuit regions formed on a device formation region in the semiconductor substrate and having a width of 0.1 to 125 &mgr;m and device isolation regions so formed on the semiconductor substrate as to isolate a plurality of circuit regions from one another and having a width of 0.01 to 2.5 &mgr;m. In such a schemed device, a ratio of the width of the device region to the width of the device isolation region is from 2 to 50. Each device isolation region is a groove formed in the semiconductor substrate by etching a portion, among the pad oxide film formed on the surface of the semiconductor substrate and a nitride film formed on the pad oxide film, existing on the device isolation region, and having a depth of from 0 to 10 nm when measured from the position of the pad oxide film on the semiconductor substrate.

Low stress semiconductor devices with thermal oxide isolation

A method of fabricating a semiconductor device is provided wherein a first semiconductor substrate is prepared with a first insulating film formed over a first main surface of the first semiconductor substrate, s semiconductor film of n-type conductivity formed over the first insulating film, and a second insulating film formed over the semiconductor film so as to cover the first main surface. A second semiconductor substrate is also prepared with a third insulating film formed over the second semiconductor substrate. Next, the second insulating film and third insulating films are bonded together by thermal processing to join the first semiconductor substrate and the second semiconductor substrate. A portion of a second main surface of said first semiconductor substrate, opposite to said first main surface of the first semiconductor substrate is then removed to expose a portion of the first semiconductor substrate, thereby providing a semiconductor layer. A gate insulating film for an MISFET is formed over the semiconductor layer; a gate electrode for the MISFET is formed over the gate insulating film, and source and drain region for the MISFET are formed in the semiconductor layer. With this arrangement, the first insulating film serves as a gate insulating film for the MISFET, and the semiconductor film serves as a gate electrode for the MISFET.

Method of manufacturing an improved SOI (silicon-on-insulator)

A semiconductor device includes a thermal oxide film for isolation, a semiconductor region that becomes an element forming region with the circumference thereof surrounded by the oxide film and diffused resistance layers in the semiconductor region and provides a structure for controlling resistance value variation of diffused resistors originated in a stress generated at time of forming the oxide film for isolation. A distance between an end portion on a longer side closest to a thermal oxide film of the diffused layer and an end of the thermal oxide film is apart from each other by a predetermined value determined by stress distribution in the semiconductor region or by at least 4 .mu.m or more, the longitudinal direction of the diffused layer portion formed from the end of the thermal oxide film over to a stress distribution (gradient) forming region in the semiconductor region is parallel to the forming direction of the stress gradient, and resistance value distribution is formed parallel to the stress gradient in the diffused layer formed from the end of the thermal oxide film over to the stress distribution forming region in the semiconductor region.

Semiconductor device having circuit element in stress gradient region by

A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Semiconductor memory

Semiconductor Memory

A bipolar device having a level difference between the contact area level of a base electrode and a base region in a silicon substrate, and the contact area level of an emitter electrode and an emitter region in the silicon substrate in the range of 0.03 .mu.m to 0.1 .mu.m by removing undesirable impurities from the emitter region and a predetermined horizontal distance between a sidewall and a device isolation film does not generate dislocation and show good electric characteristics.

Process for producing a bipolar device

Bipolar device and production thereof

A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed irk the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Growing community of inventors

Tokyo, Japan

Hiroo Masuda