Sumitomo Electric Industries, Limited

Other

Fuji Electric Co., Ltd.

Hiromu Shiomi

Yoshiki Nishibayashi

Naoji Fujimori

Shin-ichi Shikata

Takahiro Imai

Hideaki Nakahata

Yoshiaki Kumazawa

Keiji Wada

Makoto Kiyama

Kenji Fukuda

Yu Saitoh

Hideto Tamaso

Takashi Tsuno

Naoki Ooi

Shigehiro Nishino

Hidenori Kitai

Takeyoshi Masuda

Toru Hiyoshi

Nobuhiro Ota

Tsunenobu Kimoto

Hirohisa Saito

Hiroyuki Matsunami

Kazuhide Sumiyoshi

Satomi Itoh

Seiji Nakahata

Yusuke Kobayashi

Shinsuke Harada

Shinsuke Fujiwara

Akimasa Kinoshita

Akihiro Hachigo

Tsutomu Hori

Hiroyuki Kinoshita

Masami Tatsumi

Katsuko Yamamoto

Tadashi Tomikawa

Shinya Kyogoku

Yasuo Namikawa

Ryosuke Kubota

Tomihito Miyazaki

Mitsuru Shimazu

Katsuyuki Tanaka

Takaya Miyase

Takahisa Iguchi

Maoji Fujimori

A silicon carbide epitaxial layer includes a first silicon carbide layer, a second silicon carbide layer, a third silicon carbide layer, and a fourth silicon carbide layer. A nitrogen concentration of the second silicon carbide layer is increased from the first silicon carbide layer toward the third silicon carbide layer. A value obtained by dividing, by a thickness of the second silicon carbide layer, a value obtained by subtracting a nitrogen concentration of the first silicon carbide layer from a nitrogen concentration of the third silicon carbide layer is less than or equal to 6×10cm. Assuming that the nitrogen concentration of the third silicon carbide layer is N cmand a thickness of the third silicon carbide layer is X μm, X and N satisfy a Formula 1.

Silicon carbide epitaxial substrate and silicon carbide semiconductor device

A silicon carbide substrate includes a first impurity region having a first conductivity type, a second impurity region having a second conductivity type, a third impurity region having the first conductivity type, and a fourth impurity region provided between a second main surface and a bottom surface and having the second conductivity type. The first impurity region has a first region being in contact with the second impurity region and having a first impurity concentration, a second region being continuous to the first region, provided between the first region and the second main surface, and having a second impurity concentration lower than the first impurity concentration, and a third region being continuous to the first region and having a third impurity concentration higher than the first impurity concentration. A side surface is in contact with the third region, the second impurity region, and the third impurity region.

Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device

A semiconductor device includes a first JTE region formed around an active portion, a second JTE region formed around the first JTE region, and a third JTE region formed around the second JTE region. The first, second, and third JTE regions are doped with an impurity of a second conductivity type different from a first conductivity type. A concentration ratio R'(concentration of impurity in second JTE region)/(concentration of impurity in first JTE region)' and a concentration ratio R'(concentration of impurity in third JTE region)/(concentration of impurity in second JTE region)' are 0.50 or greater and 0.65 or less. A width Wof the first JTE region, a width Wof the second JTE region, and a width Wof the third JTE region are 130 &#x3bc;m or greater and 190 &#x3bc;m or less.

Schottky semiconductor device with junction termination extensions

The silicon carbide substrate includes a first impurity region, a second impurity region, and a third impurity region. The first impurity region includes: a first region in contact with the second impurity region; a second region that is in contact with the first region, that is located opposite to the second impurity region when viewed from the first region, and that has an impurity concentration higher than an impurity concentration of the first region; and a third region that is in contact with the second region, that is located opposite to the first region when viewed from the second region, and that has an impurity concentration lower than the impurity concentration of the second region. The gate insulating film is in contact with the first region, the second impurity region, and the third impurity region at a side portion of a trench.

Silicon carbide semiconductor device, and method for manufacturing same

The second conductivity type thin film includes: a high-concentration layer having a first impurity concentration; a first electric field relaxing layer continuous to the high-concentration layer at an outer circumference of the high-concentration layer, the first electric field relaxing layer having a second impurity concentration lower than the first impurity concentration; a second electric field relaxing layer continuous to the first electric field relaxing layer at an outer circumference of the first electric field relaxing layer, the second electric field relaxing layer having a third impurity concentration lower than the second impurity concentration; and a first electric field diffusion layer continuous to the second electric field relaxing layer at an outer circumference of the second electric field relaxing layer, the first electric field diffusion layer having a fourth impurity concentration lower than the third impurity concentration.

Semiconductor device

The current diffusion layer is interposed between the divided portions of the first base region. The second base region is provided adjacent to both sides of the trench current diffusion layer. The body region is provided on the trench current diffusion layer and the second base region. The source region is provided on the body region. The trench is provided to extend from a surface of the source region to the trench current diffusion layer through the source region and the body region. The trench has a bottom surface that is separated from and overlaps with the center portion of the first base region in a perpendicular direction. A width of the center portion in a horizontal direction is larger than a width of the bottom surface of the trench.

Silicon carbide semiconductor device

An active region through which current flows in a semiconductor device includes an n-type silicon carbide epitaxial layer formed on a front surface of an n-type silicon carbide semiconductor substrate; a p-type layer becoming a channel region; a trench formed so as to be in contact with a p-type layer and having an oxide film and a gate electrode embedded therein; a p-type layer arranged beneath the trench and between trenches; an n-type layer in contact with the p-type layer, a p-type layer, and the trench, and arranged in contact with a p-type layer or on a surface side of the semiconductor substrate; an n-type layer in contact with the n-type silicon carbide epitaxial layer and the p-type layer, and having an impurity concentration higher than that of the n-type layer and that of the n-type silicon carbide epitaxial layer.

Semiconductor device and method of manufacturing semiconductor device

In a first main surface of a silicon carbide substrate, a second trench having a second side surface which connects to the first main surface and is in contact with a third impurity region and a second impurity region and a second bottom portion continuous to the second side surface is formed. A fourth impurity region has a first region arranged between a second main surface and the second impurity region and a second region connecting the second bottom portion of the second trench and the first region to each other. A first electrode is electrically connected to the third impurity region on a side of the first main surface and is in contact with the second region at the second bottom portion of the second trench.

Silicon carbide semiconductor device and method for manufacturing the same

A fourth impurity region includes a first region facing a bottom portion of a trench and a part of a second impurity region and a second region facing the second impurity region. A first impurity region includes a third region in contact with a side surface of the trench, the second impurity region, the first region, and a second region and a fourth region which is located on a side of a second main surface relative to the third region, electrically connected to the third region, and lower in impurity concentration than the third region. A surface of the first region facing the second main surface is located on the side of the second main surface in a direction perpendicular to the second main surface relative to a surface of the second region facing the second main surface.

A first impurity region is formed by ion implantation through a first opening formed in a mask layer. By depositing a spacer layer on an etching stop layer on which the mask layer has been provided, a mask portion having the mask layer and the spacer layer is formed. By anisotropically etching the spacer layer, a second opening surrounded by a second sidewall is formed in the mask portion. A second impurity region is formed by ion implantation through the second opening. An angle of the second sidewall with respect to a surface is 90&#xb0;&#xb1;10&#xb0; across a height as great as a second depth. Thus, accuracy in extension of an impurity region can be enhanced.

Method of manufacturing silicon carbide semiconductor device

A method for manufacturing a semiconductor device includes the steps of: preparing a substrate made of silicon carbide; forming, on one main surface of the substrate, a detection film having a light transmittance different from that of silicon carbide; confirming presence of the substrate by applying light to the detection film; and forming an active region in the substrate whose presence has been confirmed.

Method for manufacturing semiconductor device

A method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is heated in an atmosphere containing oxygen, so as to form a gate insulating film on and in contact with the silicon carbide substrate. The silicon carbide substrate having the gate insulating film is heated at 1250&#xb0; C. or more in an atmosphere containing nitrogen and nitrogen monoxide. A value obtained by dividing partial pressure of the nitrogen monoxide by a total of partial pressure of the nitrogen and the partial pressure of the nitrogen monoxide in the second heating step is more than 3% and less than 10%. Accordingly, there can be provided a method for manufacturing a silicon carbide semiconductor device having high mobility.

Method for manufacturing silicon carbide semiconductor device

A method of cleaning a SiC semiconductor includes the steps of forming an oxide film at the surface of a SiC semiconductor, and removing the oxide film. At the step of forming an oxide film, an oxide film is formed using ozone water having a concentration greater than or equal to 30 ppm. The forming step preferably includes the step of heating at least one of the surface of the SiC semiconductor and the ozone water. Thus, there can be obtained a method of cleaning a SiC semiconductor that can exhibit cleaning effect on the SiC semiconductor.

Method of cleaning silicon carbide semiconductor

A method for manufacturing a silicon carbide semiconductor device includes the step of forming a mask pattern of a silicon oxide film by removing a portion of the silicon oxide film by means of etching employing a gas containing oxygen gas and at least one fluorine compound gas selected from a group consisting of CF, CF, CF, and SF.

There is provided a method for manufacturing a SiC semiconductor device achieving improved performance. The method for manufacturing the SiC semiconductor device includes the following steps. That is, a SiC semiconductor is prepared which has a first surface having at least a portion into which impurities are implanted. By cleaning the first surface of the SiC semiconductor, a second surface is formed. On the second surface, a Si-containing film is formed. By oxidizing the Si-containing film, an oxide film constituting the SiC semiconductor device is formed.

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Osaka, Japan

Hiromu Shiomi