Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Screen Holdings Co., Ltd.

Hiroki Taniguchi

Hidetoshi Nishimura

Masaki Tamaru

Hideaki Kondo

Ritsuko Ozoe

Takayoshi Tanaka

Tetsurou Toubou

Masaya Hirose

Akihiko Taki

Kinya Daio

Masafumi Inoue

Katsuya Fujimura

Yuta Nakano

Yoichi Matsumura

Hiroyuki Shimbo

Takako Ohashi

Hisako Yoneda

Chihiro Itoh

Masuko Taniguchi

Kazunari Ikeda

Takahisa Tokushige

A substrate processing device includes a substrate holding table, an ultraviolet irradiator, a tubular member, a first gas supplying unit, and a second gas supplying unit. The ultraviolet irradiator is disposed facing to the substrate through an active space and configured to irradiate the substrate with ultraviolet light. The tubular member includes an inner surface surrounding a side surface of the substrate holding table, and at least one opening at a position facing to the side surface on the inner surface. The first gas supplying unit supplies gas to a space between the side surface of the substrate holding table and the inner surface of the tubular member through the at least one opening. The second gas supplying unit supplies gas to an active space between the substrate and the ultraviolet irradiator.

Substrate processing device, substrate processing method, and substrate processing system

There is provided a layout structure of a semiconductor integrated circuit capable of preventing the thinning of a metal wiring line close to a cell boundary and wire breakage therein without involving increases in the amount of data for OPC correction and OPC process time. In a region interposed between a power supply line and a ground line each placed to extend in a first direction, first and second cells each having a transistor and an intra-cell line each for implementing a circuit function are placed to be adjacent to each other in the first direction. In a boundary portion between the first and second cells, a metal wiring line extending in a second direction orthogonal to the first direction is placed so as not to short-circuit the power supply line and the ground line.

Semiconductor integrated circuit device having a dummy metal wiring line

This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.

Standard cell and semiconductor device including the same

A semiconductor deviceincludes a normal circuitand a voltage fluctuation detection circuitconnected to a power supplyin common with the normal circuit. The voltage fluctuation detection circuitincludes an inverting amplifier, a switching element, which is connected between input and output terminals of the inverting amplifier, and a capacitance elementconnected to the input terminal of the inverting amplifier. After the normal circuitand the switching elementare set to an operating state and ON state, respectively, when the switching elementis set to OFF state at an arbitrary time, charge corresponding to a power supply voltage Vcat that time accumulates in the capacitance element. After the normal circuitis set to a suspended state, a potential VDD of the power supplyis set to an arbitrary value, and the inverting amplifiercompares the value of a power supply voltage Vc with the voltage value Vccorresponding to the charge held in the capacitance element

Semiconductor device

In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cellon the clock path, and no cell for performing a logical operation is placed in this cell-placement prohibiting area. Also, a cell-placement prohibiting area may be set for each of cell groups formed of a plurality of cells closely placed together. Furthermore, a capacitive cell may be placed in the cell-placement prohibiting area.

Semiconductor integrated circuit and method of designing the same

A scan flip-flop circuit has a scan test data output terminal QT in addition to a Q terminal and a /Q terminal. To the QT terminal, the data that have been held in an internal data holding circuit is transferred via a tristate buffer that has been incorporated in advance. The drive capability of the tristate buffer is determined so that a propagation delay time is obtained and the scan test data outputted from the QT terminal is propagated to the scan test data input terminal DT of the next stage scan flip-flop circuit. Consequently, during scan testing, a sufficient delay is added to the output from the scan flip-flop circuit, and hold errors do not easily occur.

Scan flip-flop circuit, logic macro, scan test circuit, and method for laying out the same

Growing community of inventors

Kyoto, Japan

Hiroki Taniguchi