Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Renesas Technology Corp.

Hiroki Shinkawata

Takashi Terauchi

Yasushi Hashizume

Tatsuyoshi Mihara

Hitoshi Maeda

Tatsuo Kasaoka

Shinya Soeda

Yoshikazu Ohno

Hiroyasu Nohsoh

Takahiro Yokoi

Kouta Inoue

Gate patterns are formed on a semiconductor layer and a conductive film is formed on the semiconductor layer so as to cover the gate patterns. By performing a polishing process to the conductive film and patterning the polished conductive film, pad layers are formed between the gate patterns via sidewall spacers.

Method of manufacturing semiconductor device

In an SOI substrate having a semiconductor substrate serving as a support substrate, an insulating layer on the semiconductor substrate and a semiconductor layer on the insulating layer, an element isolation region which penetrates the semiconductor layer and the insulating layer and whose bottom part reaches the semiconductor substrate is formed, and a gate electrode is formed on the semiconductor layer via a gate insulating film. A divot is formed in the element isolation region at a position adjacent to the semiconductor layer, and a buried insulating film is formed in the divot. The gate electrode includes a part formed on the semiconductor layer via the gate insulating film, a part located on the buried insulating film and a part located on the element isolation region.

Semiconductor device and manufacturing method thereof

A semiconductor device reduces measurement time. The semiconductor device according to an embodiment of the invention includes: plural series-coupled resistance elements for testing; plural switches coupled to a coupling path coupling the resistance elements; and plural selection circuits to select, by turning on or off the switches, a number of the series-coupled resistance elements to be measured as a group. In the semiconductor device: the switches include plural first switches coupled to plural groups of the resistance elements, each of the groups including N (N=2 or a larger integer) of the resistance elements; and the selection circuits turn the first switches on or off and thereby select a number of the series-coupled resistance elements to be measured as a group, the number equaling the N.

Semiconductor device and semiconductor device measuring method

A semiconductor device including a semiconductor substrate having a logic formation region where a logic device is formed; a first impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in the logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a second silicide film formed in an upper surface of the fourth impurity region and having a larger thickness than the first silicide film.

Semiconductor device and semiconductor device manufacturing method

The present invention, in a method for manufacturing a semiconductor device having an n-channel transistor and a p-channel transistor each of which has an insulation film of a high electric permittivity, inhibits a foreign matter from adhering to the side of a gate insulation film of the n-channel transistor. Over the main surface of a semiconductor substrate, a functional n-channel transistor is formed in a p-type impurity region and a functional p-channel transistor is formed in an n-type impurity region. A plurality of first peripheral transistors formed in the region other than the functional n-channel transistor in the p-type impurity region are formed so that a peripheral n-type structure and a peripheral p-type structure may coexist in a planar view.

To provide a manufacturing method of a semiconductor device capable of placing a larger number of alignment marks for lithography and PCM and at the same time, preventing information leakage from the PCM. In a portion of a first scribe region sandwiched between first semiconductor chip regions, a first region and a second region are placed in parallel to each other. The first region is equipped with at least one monitor selected from a first monitor for electrically evaluating at least either one of an active element (such as transistor) and a passive element (such as resistor or capacitor), a second monitor for dimensional control, and a third monitor for measuring film thickness. In the second region, an alignment mark for lithography is placed. In the cutting step, the first region is cut off.

Manufacturing method of semiconductor device

The present invention aims to increase the number of test elements of a TEG without increasing the area of each of slice areas. Test electrode pads are disposed in alignment in one row in each of areas separated from semiconductor chips provided over a semiconductor wafer. Test elements are formed corresponding to these test electrode pads and in areas lying directly therebelow. Electrode terminals of the test elements are electrically coupled to the test electrode pads adjacent to the corresponding electrode pads and the test electrode pads further adjacent thereto with being spaced one test electrode pad apart. Upon testing, probe pins are brought into contact with the odd-numbered test electrode pads to conduct testing. Next, the probe pins are brought into contact with the even-numbered test electrode pads while being shifted by one electrode pad pitch thereby to conduct testing.

Manufacturing method of a semiconductor device, a semiconductor wafer, and a test method

A semiconductor device including a semiconductor substrate having a logic formation region in which a memory device is formed and a logic formation region in which a logic device is formed; a first impurity region formed in an upper surface of said semiconductor substrate in the logic formation region; a second impurity region formed in an upper surface of the semiconductor substrate in said logic formation region; a third impurity region formed in an upper surface of the first impurity region and having a conductivity type different from that of the second impurity region; a fourth region formed in an upper surface of the second impurity region and having a conductivity type different from that of the second impurity region; a first silicide film formed in an upper surface of the third impurity region; a capacitor formed above the first silicide film and electrically connected to the first silicide film; and a second silicide film formed in an upper surface of the fourth impurity region and having a larger thickness than the first silicide film; wherein the first and second silicide films include cobalt.

High speed memory device with reduced resistance and leakage current

A semiconductor technique is provided which can achieve both of lowered resistance in a logic formation region and reduced leakage current of the capacitor of a memory device. Source/drain regions () are formed in the upper surface of a semiconductor substrate () in a memory formation region and cobalt silicide films () are formed in the upper surfaces of the source/drain regions (). Source/drain regions () are formed in the upper surface of the semiconductor substrate () in a logic formation region and cobalt silicide films () are formed in the upper surfaces of the source/drain regions (). The cobalt silicide films () in the logic formation region are thicker than the cobalt silicide films () in the memory formation region.

Semiconductor device having memory and logic devices with reduced resistance and leakage current

A first metal film, a first interlayer insulating film, a second metal film, and a second interlayer insulating film are deposited in this order over a silicon nitride film. An opening penetrating the first and second interlayer insulating films and the first and second metal films is created, whereby a contact metal, to hold a to-be-formed lower electrode thereon, is exposed. A metal film is provided to cover the second interlayer insulating film. The opening is filled with the metal film. A main part and the uppermost fin (namely, the fin farthest from a substrate) of a lower electrode, are formed by the same process.

Growing community of inventors

Tokyo, Japan

Hiroki Shinkawata