Toyota Jidosha Kabushiki Kaisha

Denso Corporation

Mirise Technologies Corporation

Denso Corpora Tion

Kyoto Institute of Technology

Hiroki Miyake

Tatsuji Nagaoka

Shuhei Ichikawa

Sachiko Aoi

Yukihiko Watanabe

Yusuke Yamashita

Yasushi Urakami

Shinichiro Miyahara

Katsuhiro Kutsuki

Atsuya Akiba

Masahiro Yoshimoto

Hiroyuki Nishinaka

Keita Kataoka

Yoshitaka Nagasato

Daigo Kikuta

Yuki Kajita

In a surface treatment method for a gallium oxide-based semiconductor substrate, a surface of the gallium oxide-based semiconductor substrate is flattened by dry etching with a self-bias of 150 V or more. After the surface of the gallium oxide-based semiconductor substrate is flattened, the surface of the gallium oxide-based semiconductor substrate is washed with a chemical solution containing HSOto expose a step terrace structure on the surface of the gallium oxide-based semiconductor substrate.

Surface treatment method for gallium oxide-based semiconductor substrate and semiconductor device

A method for manufacturing a semiconductor device includes: preparing a substrate made of a compound semiconductor containing a first element and a second element that is bonded to the first element and has an electronegativity smaller than that of the first element by 1.5 or more; causing an electric current to flow in the substrate; and dividing the substrate at a position including a current region where the electric current is caused to flow and along a cleavage plane of the substrate. A method for manufacturing a semiconductor device includes: stacking a first substrate and a second substrate each made of the compound semiconductor; and bonding the first substrate and the second substrate by causing an electric current to flow between the first substrate and the second substrate.

Method for manufacturing semiconductor device

A semiconductor device includes: a first semiconductor layer having an N conductive type and made of a gallium oxide-based semiconductor; and a second semiconductor layer made of a gallium oxide-based semiconductor, in contact with the first semiconductor layer, and having the N conductive type with an electrically active donor concentration higher than an electrically active donor concentration of the first semiconductor layer. A difference between a donor concentration of the first semiconductor layer and a donor concentration of the second semiconductor layer is smaller than a difference between the electrically active donor concentration of the first semiconductor layer and the electrically active donor concentration of the second semiconductor layer.

A semiconductor device includes: a p-type region including a super-lattice pseudo mixed crystal region in which a first layer and a second layer are alternately stacked. The first layer includes a gallium oxide based semiconductor. The second layer includes a p type semiconductor made of a material different from the first layer.

P-type gallium oxide semiconductor device with alternating layers

A manufacturing method of a semiconductor device includes: preparing a semiconductor substrate including a first semiconductor layer made of gallium oxide containing Sn and a second semiconductor layer disposed on the first semiconductor layer and made of n type gallium oxide having a Sn concentration lower than a Sn concentration of the first semiconductor layer; implanting ions of a group 2 element into the second semiconductor layer; and forming a diffusion region, in which the group 2 element diffuses, in a range from a surface of the second semiconductor layer to an interface between the second semiconductor layer and the first semiconductor layer.

Manufacturing method of semiconductor device

A method for manufacturing a semiconductor device having a gallium oxide-based semiconductor layer includes: ion-implanting dopant into a gallium oxide-based semiconductor layer while heating the gallium oxide-based semiconductor layer; and annealing the gallium oxide-based semiconductor layer under an oxygen atmosphere, after the ion-implanting.

Method for manufacturing semiconductor device having gallium oxide-based semiconductor layer

Semiconductor device and method for manufacturing the same

A wafer processing apparatus is configured to process a wafer by supplying mist to a surface of the wafer. The wafer processing apparatus includes a furnace in which the wafer is disposed, a gas supplying device configured to supply gas into the furnace, a mist supplying device configured to supply the mist into the furnace, and a controller. The controller is configured to execute a processing step by controlling the gas supplying device and the mist supplying device to supply the gas and the mist into the furnace, respectively. The controller is further configured to control the mist supplying device to stop supplying the mist into the furnace while controlling the gas supplying device to keep supplying the gas into the furnace when the processing step ends.

Wafer processing apparatus and method for processing wafer

A semiconductor apparatus has a semiconductor substrate, a first trench provided in a front surface of the semiconductor substrate, an anode electrode provided inside the first trench, and a cathode electrode provided on a back surface of the semiconductor substrate. The semiconductor substrate has a first p-type region, a second p-type region, and a main n-type region which is in contact with the first p-type region and the second p-type region, and is in Schottky contact with the anode electrode in the side surface of the first trench. The semiconductor substrate satisfies the relationship that an area of the first trench, when the front surface is viewed in a plan view, is smaller than an area of a Schottky interface where the main n-type region is in contact with the anode electrode in the side surface of the first trench.

Semiconductor apparatus

A power conversion device includes a first switching element configured by using a first semiconductor material and a second switching element connected in parallel with the first switching element and configured by using a second semiconductor material having a band gap narrower than that of the first semiconductor material. The power conversion device further includes a control device configured to selectively execute any one of first switching control and second switching control of intermittently turning on the first switching element and the second switching element, respectively, according to a current command value. A size of the first switching element is smaller than a size of the second switching element. The control device selects the first switching control if the current command value is smaller than a first threshold value and selects the second switching control if the current command value is larger than a second threshold value.

Power conversion device

A power converter includes one or more first conversion circuits, one or more second conversion circuits, and a controller. The first conversion circuit is configured to use a trench type transistor. The second conversion circuit is configured to use a planar type transistor. All the one or more first conversion circuits and all the one or more second conversion circuits are connected in parallel to each other or connected in series to each other. The controller stops all the one or more second conversion circuits and operates at least one of the one or more first conversion circuits while an output command value is lower than a predetermined output threshold value. The controller operates all the one or more first conversion circuits and operates at least one of the one or more second conversion circuits when the output command value exceeds the predetermined output threshold value.

Power converter with trench and planar transistors to improve efficiency

A technique stabilizing properties of SBDs is provided. An SBD is provided with a p-type contact region in contact with an anode electrode, and an n-type drift region in Schottky contact with the anode electrode. The p-type contact region includes a first p-type region having a corner portion, a second p-type region connected to the corner portion, and an edge filling portion located at a connection between the first p-type region and the second p-type region. First and second extended lines intersect at an acute angle, where the first extended line is a line extended from a contour of the first p-type region toward the connection and the second extended line is a line extended from a contour of the second p-type region toward the connection. An acute angle edge formed between the first extended line and the second extended line is filled with the edge filling portion.

Schottky barrier diode and manufacturing method thereof

A Schottky barrier diode provided herein includes: a semiconductor substrate; and an anode electrode being in contact with the semiconductor substrate. The semiconductor substrate includes: p-type contact regions being in contact with the anode electrode; and an n-type drift region being in contact with the anode electrode by Schottky contact in a range where the p-type contact regions are not provided The p-type contact regions includes: a plurality of circular regions located so that the circular regions are arranged at intervals between an outer side and an inner side at a contact surface between the semiconductor substrate and the anode electrode; and an internal region located in an inner portion of the circular region located on an innermost side at the contact surface and connected to the circular region located on the innermost side at the contact surface.

Schottky barrier diode and method for manufacturing the same

An SBD includes a semiconductor substrate; an anode electrode which is in Schottky contact with a front surface of the semiconductor substrate; and a cathode electrode which is in ohmic contact with a rear surface of the semiconductor substrate. A trench extending from the front surface of the semiconductor substrate toward the rear surface of the semiconductor substrate is provided in the semiconductor substrate, and an inner surface of the trench is covered with an insulating film. An insulating layer is deposited at a deep portion of the trench, and a conductive layer is deposited at a shallow portion of the trench. An n-type front surface region in contact with the anode electrode, an n-type rear surface region in contact with the cathode electrode, and an n-type intermediate region connecting the front surface region and the rear surface region are provided in the semiconductor substrate.

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Toyota, Japan

Hiroki Miyake