Hitachi, Ltd.

Rising Silicon, Inc.

Hirokazu Ihara

Kinji Mori

Shoji Miyamoto

Nobuyasu Kanekawa

Tetsuya Okishima

Kiyoshi Kawabata

Hisayoshi Yamanaka

Masatsugu Akiyama

Makoto Nohmi

Seiji Yasunobu

Sadanori Shingai

Katsumi Kawano

Nobuyuki Fujikura

Hiroshi Matsumaru

Masakazu Akiyama

Katuaki Ikeda

Yuko Kunai

Tadaaki Kadoya

Masayuki Orimo

Yasuo Suzuki

Hiroyuki Kaji

Masaharu Tadauchi

Nobuhisa Kobayashi

Kunio Hiyama

Yoshihiko Nitta

Kazuo Kera

Yutaka Kubo

Masaya Yamamoto

Yoshinori Kawai

Shigehiro Tomita

Minoru Hatada

Kazumasa Sugiura

Masahiro Yasunami

Masaharu Yabushita

Ryota Kaijima

Hisao Kuma

Makoto Noomi

Hatsuhiko Kato

Kouhei Kato

Yoko Kunai

An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having a checking function for detecting faults of the processor.

Electronic circuit package

An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.

Semiconductor multi-chip module

An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayer. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the is surface of the insulating layer, in order to use a portion of the multilayer wing substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line are formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line are formed on the other side of the wiring substrate.

Electronic circuit package including plural semiconductor chips formed

An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wire bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayer element. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, thereby making it possible to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground. The bus line preferably includes two data bus lines, the semiconductor chips connected with one data bus line being formed on one side of the wiring substrate and the semiconductor chips connected with the other data bus line being formed on the other side of the wiring substrate.

Electronic circuit package including plural bare chips mounted on a

A plurality of spacecrafts having their own functions are each provided with a communication controller and its own mission, and communicate with each other to perform specific operations. In addition, a plurality of units having particular functions are housed in a system dock, and arbitrary ones of these units are combined to constitute a spacecraft according to the use. Units responsible for performing the specific operations are interchangeably connected, so as to be separable from the individual spacecraft.

Spacecraft system

A plurality of processors have a plurality pairs of input ports and output ports, and are constituted in a looped manner by connecting the output ports and the input ports of the same pairs of any number of processors. A transmission system is formed in which the data on the same loop is allowed to flow and the data that is required is transferred to different loops, so that the data flows through the loops and across the loops to reach a predetermined processor. The system is formed of a first group of looped transmission lines, a second group of looped transmission lines that are arranged to intersect said first group of looped transmission lines, transmission lines that couple said intersecting transmission lines together, and a data processing and controlling unit that controls the transmission of data among the transmission lines and that processes the data.

Multi-dimensional structured computer system

In order to recognize an object to be recognized, the present invention comprises a plurality of photosensors for receiving reflected rays from an object to be recognized, and a plurality of image recognition processors. Said plurality of sensors and processors are connected in network structure, so that each of said plurality of sensors recognizes only a part of the object to be recognized and applies signals to said plurality of image recognition processors, and each of said plurality of image recognition processors recognizes the object to be recognized according only to said image recognition signals applied from said plurality of sensors adjacent to each other. Further, in order to make the image of the object, each of said image recognition processor recognizes the image of the object, in conjunction with adjacent image recognition processors, according to the information showing the profile of each part of the object, and applies signals to light emitting devices for displaying the image.

Image processing apparatus

Input signals supplied to a plurality redundant subsystems are input to an output selecting circuit after an output of a subsystem is changed from an output signal of a subsystem having a most reliable output signal to another output signal of another subsystem having a lower reliable output signal in turn using self-diagnoses and cross-diagnoses in each subsystem according to an algorithm as follows:

Fault tolerant system employing majority voting

Growing community of inventors

Machida, Japan

Hirokazu Ihara