Kabushiki Kaisha Toshiba

Ebara Corporation

Other

Hirokazu Ezawa

Masahiro Miyata

Hiroaki Inoue

Tatsuo Migita

Hisashi Kaneko

Manabu Tsujimura

Soichi Yamashita

Takashi Togasaki

Makoto Honda

Yukio Ikeda

Mie Matsuo

Tadashi Iijima

Naoaki Ogure

Kaori Yomogihara

Kenji Nakamura

Takashi Endo

Soichi Homma

Kenro Nakamura

Hideaki Harakawa

Hideto Matsuyama

Moriji Matsumoto

Masanori Numano

Toshiaki Idaka

Hidemitsu Egawa

Takahito Nagamatsu

Kazuhiro Murakami

Takeyuki Ohdaira

Hideo Aoki

Ichiro Omura

Yoichiro Kurita

Kenji Takahashi

Atsuko Sakata

Kazuyuki Higashi

Chiaki Takubo

Takamasa Usui

Kazushige Kawasaki

Atsushi Shigeta

Kenichi Matsushita

Sachiyo Ito

Tomio Katata

Junichiro Yoshioka

Hideo Numata

Satoshi Tsukiyama

Masayuki Uchida

Seiichi Omoto

Takeo Kubota

Tadayoshi Watanabe

Takashi Yoda

Masaya Shima

Susumu Harada

Tsuyoshi Tokuoka

Hitomi Yamaguchi

Tatsuo Shiotsuki

Hiroshi Ikenoue

Masaharu Seto

Johta Fukuhara

Koro Nagamine

Masako Morita

Kiyoshi Muranishi

Shinzi Takeda

Takeyuki Odaira

Toru Matanabe

A method of manufacturing a semiconductor device includes forming an opening in a first substrate and filling the opening with a metal to form a first connection electrode. The first substrate is then polished by chemical mechanical polishing under conditions such that a polishing rate of the metal is less that of the region surrounding the metal. The chemical mechanical polishing thereby causes the first connection electrode to protrude from the surface of the first substrate. The first substrate is stacked with a second substrate having a second connection electrode. The first and second connection electrodes are bonded by applying pressure and heating to a temperature that is below the melting point of the metal of the first connection electrode.

Semiconductor device and manufacturing method thereof

According to one embodiment, the first resin layer is provided on the first face of the upper layer chip. The first interconnect layer is electrically connected to the upper layer chip. The second resin layer extends into a region outside chip. The region is outer side of a side face of the upper layer chip. The second interconnect layer is provided in the second resin layer. The second interconnect layer is connected to the first interconnect layer and extending into the region outside chip. The lower layer chip is mounted on the surface side of the first resin layer, and is connected to the first interconnect layer. The first sealing resin covers the upper layer chip.

Semiconductor device having fan-in and fan-out redistribution layers

According to one embodiment, a semiconductor substrate, a redistribution trace, and a surface layer are provided, with the surface layer provided on the redistribution trace. On the semiconductor substrate, a wire and a pad electrode are formed. The redistribution trace is formed on the semiconductor substrate. The surface layer is larger in width than the redistribution trace, and extends beyond the edge of the redistribution trace.

Bump structure with underbump metallization structure and integrated redistribution layer

An electronic component in which an element is formed on a chip includes: a pad that is made of a conductive material and that is formed in a first bump formation region that is two-dimensionally arranged in center of one principle face and in a second bump formation region that is linearly arranged at peripheral border of the principle face; a passivation film that is formed on the principle face to cover portion except a formation position of the pad; a metal layer that is formed on the pad; and a bump that is made of a conductive material and that is formed on the metal layer by plating, wherein radius of the metal layer in the second bump formation region is smaller than radius of at least some of the metal layer in the first bump formation region.

Electronic component and method of connecting with multi-profile bumps

According to one embodiment, a semiconductor substrate, a metal film, a surface modifying layer, and a redistribution trace are provided. On the semiconductor substrate, a wire and a pad electrode are formed. The metal film is formed over the semiconductor substrate. The surface modifying layer is formed on a surface layer of the metal film and improves the adhesion with a resist pattern. The redistribution trace is formed on the metal film via the surface modifying layer.

Semiconductor device and manufacturing method of semiconductor device

A first conducting layer is formed on a side of a main surface on which an electrode terminal of a semiconductor device is provided in a semiconductor substrate. The first conducting layer is electrically connected to the electrode terminal of the semiconductor device. A mask layer that has an opening at a predetermined position is formed on the first conducting layer. A second conducting layer is formed inside the opening of the mask layer. The mask layer is removed. A relocation wiring that includes the first conducting layer and electrically draws out the electrode terminal is formed by performing anisotropic etching for the first conducting layer using the second conducting layer as a mask. Finally, a bump is formed on the relocation wiring by causing the second conducting layer to reflow.

Manufacturing method of semiconductor apparatus and semiconductor apparatus

According to one embodiment, a manufacturing method of a semiconductor device attained as follows. A dielectric layer having a first opening and a second opening reaching an electrode terminal is formed by modifying a photosensitive resin film on a substrate on which the electrode terminal of a first conductive layer is provided. Next, a second conductive layer that is electrically connected to the electrode terminal is formed on the dielectric layer that includes inside of the first opening, and a third conductive layer that has an oxidation-reduction potential of which difference from the oxidation-reduction potential of the first conductive layer is smaller than a difference of the oxidation-reduction potential between the first conductive layer and the second conductive layer is formed on the second conductive layer. Next, a dielectric layer having a third opening reaching the third conductive layer and a fourth opening reaching the electrode terminal via the second opening is formed by modifying a photosensitive resin film, and a bump that is electrically connected to the third conductive layer is formed.

Manufacturing method of semiconductor device and semiconductor device

An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NFor HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.

Method of manufacturing a semiconductor device from which damage layers and native oxide films in connection holes have been removed

A peripheral processing method includes: by at least one of locally heating the periphery of a workpiece including a silicon-based substrate and selectively supplying reacting activation species to the periphery, allowing oxidation rate on the periphery to be higher than oxidation rate of native oxide film on a surface of the silicon-based substrate, thereby forming a first oxide film along the periphery, the first oxide film being thicker than the native oxide film. A method of manufacturing a semiconductor device includes: forming an insulating film on a frontside and periphery of a silicon-based substrate; forming a workpiece by selectively etching away the insulating film to expose a portion of the frontside of the silicon-based substrate; forming a first oxide film at an exposed part of the silicon-based substrate, the exposed part being formed in the insulating film of the periphery during the selective etching; depositing a metal film on the frontside of the workpiece after the first oxide film is formed; and allowing the metal film to react with the portion of the frontside of the silicon-based substrate by heat treatment.

Peripheral processing method and method of manufacturing a semiconductor device

A semiconductor device which is compact and thin in size, low in resistance of a current path and parasitic inductance and excellent in reliability is provided. This semiconductor device comprises a semiconductor substrate, a first main electrode which is formed on a front surface of the semiconductor substrate, a second main electrode which is formed on a rear surface of the semiconductor substrate, and a conducting portion which is formed in a direction to pierce through the semiconductor substrate, wherein the second main electrode is extracted to the front surface of the semiconductor substrate via the conducting portion. And, the conducting portion is a through via which has a through hole formed through the semiconductor substrate in its thickness direction and a conductive portion which is formed in the through hole and connected to the second main electrode.

Semiconductor device having power semiconductor elements

According to an embodiment of the present invention, a method of manufacturing a semiconductor device, comprising forming a conducting layer on a substrate; forming a resist mask having an opening in a prescribed position on the conducting layer; forming a first plated film in the opening by supplying an electric current to the conducting layer; increasing the interval between an inner side surface of the resist mask forming the opening and the first plated film by setting back the inner side surface; and forming a second plated film in the opening resulting from the setback of the inner side surface to cover the first plated film by supplying an electric current to the conducting layer.

Method of manufacturing semiconductor device and semiconductor device

There is here disclosed a manufacturing method of a semiconductor device, comprising providing a first film by a PVD process in a recess formed in at least one insulating film, the first film containing at least one metal element belonging to any one of the groups-A,-A, and-A, continuously providing a second film by at least one of CVD and ALD processes on the first film without opening to atmosphere, the second film containing at least one metal element belonging to any one of the groups-A,-A, and-A, continuously providing a third film by the PVD process on the second film without opening to the atmosphere, the third film containing at least one metal element belonging to any one of the groups-A,-A, and-A, continuously providing a first Cu film on the third film without opening to the atmosphere, and heating the Cu film.

Manufacturing method of semiconductor device

Growing community of inventors

Tokyo, Japan

Hirokazu Ezawa