Tokyo Electron Limited

Hirokazu Aizawa

Kaoru Maekawa

Kandabara N Tapily

Nicholas Joy

Akiteru Ko

Angelique Denise Raley

Gerrit J Leusink

Kiyotaka Imai

Kai-Hung Yu

Katie Lutker-Lee

Yusuke Yoshida

Yuji Mimura

Hiroshi Maeda

Karthikeyan Pillai

Harunobu Suenaga

A method of processing a substrate that includes: etching a recess in the substrate using a metal hard mask (MHM) layer as an etch mask, the substrate including a dielectric layer over a conductive layer the includes a first conductive material, a portion of the MHM layer remaining over top surfaces of the dielectric layer after the etching; depositing a sacrificial fill over the substrate to at least partially fill the recess; removing the remaining portion of the MHM layer to expose the top surfaces while protecting the recess with the sacrificial fill; removing the sacrificial fill from the recess after removing the MHM layer, the removing of the sacrificial fill including exposing a portion of the conductive layer; and depositing a second conductive material to fill the recess, the depositing of the second conductive material providing an electrical connection between the conductive layer and the second conductive material.

Metal hard mask integration

A method for processing a substrate that includes: depositing a filling material over the substrate including a first recess and a second recess, the filling material filling the first recess and the second recess; patterning the filling material such that the first recess is reopened while the second recess remains filled with the filling material; filling the first recess with a conductive material to a first height; etching the filling material selectively to the conductive material to reopen the second recess; filling a remainder of the first recess and the second recess with the conductive material; and performing an etch back process to etch the conductive material such that the first recess and the second recess are filled with the conductive material to a second height.

Method of conductive material deposition

A self-aligned multiple patterning (SAMP) multi-color spacer patterning process is disclosed for formation of structures on substrates. Trenches and vias may be formed in the process. A trench memorization layer and a via memorization layer may be formed on the substrate. In one embodiment, the trench memorization layer and the via memorization layer are formed between the multi-color spacer patterning structures and a low-k interlayer dielectric layer. The use of the trench memorization layer and the via memorization layer allows the formation of trenches and vias in the low-k interlayer dielectric layer without causing damage to the low-k properties of the low-k interlayer dielectric layer.

Method and process using dual memorization layer for multi-color spacer patterning

Described herein is a method of bonding and/or debonding substrates. In one embodiment, at least one of the surfaces of the substrates to be bonded is comprised of an oxide. In one embodiment, the surfaces of both substrates comprise an oxide. A wet etch may then be utilized to debond the substrates by etching away the layers that have been bonded. In one embodiment, a fusion bonding process is utilized to bond two substrates, at least one substrate having a silicon oxide surface. In one exemplary etch, a dilute hydrofluoric (DHF) etch is utilized to etch the bonded silicon oxide surface, allowing for two bonded substrates to be debonded. In another embodiment, the silicon oxide may be a low density silicon oxide. In one embodiment, both substrates may have a surface layer of the low density silicon oxide which may be fusion bonded together.

Method and structure for low density silicon oxide for fusion bonding and debonding

Embodiments of systems and methods for semiconductor back end of line (BEOL) interconnect using multiple materials in a fully self-aligned via (FSAV) process. In an embodiment, a method includes receiving a substrate with a patterned structure formed on a surface of the substrate. A method may also include depositing a first interconnect material in a first region of the patterned structure. Such methods may also include depositing a second interconnect material in a second region of the patterned structure, wherein the first interconnect material is different from the second interconnect material, and wherein the first region and the second region include a common layer of the patterned structures.

Semiconductor back end of line (BEOL) interconnect using multiple materials in a fully self-aligned via (FSAV) process

A process is provided in which low-k layers are protected from etch damage by the use of a selectively formed protection layer which forms on the low-k layer. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. In one embodiment, the selectively formed protection layer may be formed by a selective deposition process which selectively forms layers on the low-k dielectric but not over the conductor layer. The selectively formed protection layer may then be utilized to protect the low-k layer from a plasma etch that is utilized to recess the conductor. In this manner, a conductor (for example metal) may be recessed in a low-k dielectric layer via a plasma etch process.

Growing community of inventors

Albany, NY, United States of America

Hirokazu Aizawa