Fujitsu Corporation

The University of Tokyo

Hiroji Ebe

Yasuhiko Arakawa

Akira Sawada

Mitsuru Sugawara

Kenichi Kawaguchi

Yoshiaki Nakata

Denis Guimard

Shiro Tsukamoto

Tomoyuki Akiyama

Ken Morito

Ayahito Uetake

Hiroshi Takigawa

Osamu Wada

Prafulla Masalkar

Takashi Kita

Mitsuru Fujitsu Limited Sugawara

The method of manufacturing the semiconductor device comprises the step of forming quantum dotson a base layerby self-assembled growth; the step of irradiating Sb or GaSb to the surface of the base layerbefore or in the step of forming quantum dots; the step of etching the surfaces of the quantum dotswith an As raw material gas to thereby remove an InSb layercontaining Sb deposited on the surfaces of the quantum dots; and growing a capping layeron the quantum dotswith the InSb layerremoved.

Method of manufacturing a semiconductor device with quantum dots formed by self-assembled growth

Method of manufacturing semiconductor device with quantum dots formed by self-assembled growth

A quantum dot semiconductor device includes an active layer having a plurality of quantum dot layers each including a composite quantum dot formed by stacking a plurality of quantum dots and a side barrier layer formed in contact with a side face of the composite quantum dot. The stack number of the quantum dots and the magnitude of strain of the side barrier layer from which each of the quantum dot layers is formed are set so that a gain spectrum of the active layer has a flat gain bandwidth corresponding to a shift amount of the gain spectrum within a desired operation temperature range.

Quantum dot semiconductor device

A semiconductor device including quantum dots comprises a barrier layer of a semiconductor crystal having a first lattice constant and a quantum dot layer including a plurality of quantum dots of a semiconductor crystal having a second lattice constant formed on the barrier layer and a side barrier layer of a semiconductor crystal having a third lattice constant, which is formed in contact with the side faces of the plurality of quantum dots, in which the barrier layer, the quantum dots and the side barrier layer are configured so that the difference between the values of the first lattice constant and the second lattice constant has a sign opposite to that of the difference between values of the first lattice constant and the third lattice constant.

Semiconductor device

A quantum semiconductor device including quantum dots formed by S-K growth process taking place in a heteroepitaxial system wherein the relationship between the energy level of light holes and the energy level of heavy holes in the valence band is changed by optimizing the in-plane strain and the vertical strain accumulated in a quantum dot.

Quantum optical semiconductor device

A semiconductor optical device having a substrate having a surface of a first semiconductor having a first lattice constant; and a semiconductor lamination layer formed on the substrate, the semiconductor lamination layer having an active layer which contains quantum dots of a first kind made of a second semiconductor having a second lattice constant in bulk state smaller than the first lattice constant. The active layer may contain quantum dots of a second kind made of a third semiconductor having a third lattice constant in bulk state larger than the first lattice constant. The quantum dots of the first and second kinds are preferably disposed alternately along the thickness direction between the barrier layers having the first lattice constant.

Semiconductor optical device with quantum dots having internal tensile or compressive strain

A first multi-quantum well structure is formed on a GaAs substrate . The first multi-quantum well structure is formed of an AlGaAs barrier layer and a GaAs well layer alternately laid one on the other to form a multi-quantum well. The GaAs barrier layer is not doped with an impurity. A second multi-quantum well structure is formed on the first multi-quantum well structure . The second multi-quantum well structure is formed of an AlGaAs barrier layer and a GaAs well layer alternately laid one on the other to form a multi-quantum well. The GaAs barrier layer is not doped with an impurity. Whereby a required electrode area can be smaller to thereby obtain higher detection sensitivity.

Photodetecting device

A method and apparatus in which separate steps are used between feeding source gases and growing films in a process of chemical vapor deposition (CVD) for compound semiconductor films. In one embodiment, a CVD reactor chamber has a piston which can change the volume of the chamber to control the pressure of the source gases therein. After source gases are fed to the chamber having a substrate under the condition that no CVD takes place due to an insufficient vapor pressure, the chamber is kept closed for a few seconds, and then pressurized by the piston to start CVD. A typical result indicates that a Hg.sub.1-x Cd.sub.x Te (where x=0.2) film on a 3-inch CdTe wafer has only 1% (or .DELTA.x=0.002) inhomogeneity in composition.

Method for chemical vapor deposition of semiconductor films by separate

A group II-VI epitaxial layer grown on a (111) silicon substrate has a lattice mismatch which is minimized, as between the group II-VI epitaxial layer and the silicon substrate. The grown group II-VI epitaxial layer also has a (111) plane at the interface with the substrate, and a 30.degree. in-plane rotation slip is formed at the interface between the (111) silicon substrate and the group II-VI epitaxial layer. The above structure is produced by a metal organic chemical vapor deposition method (MOCVD), in which a mol ratio of a group VI gas source supply to a group II gas source supply is kept greater than 15 during the growth. The (111) silicon substrate is preferably mis-oriented toward the &lt;110&gt; direction of the silicon substrate. When a HgCdTe layer is grown on the epitaxial layer, the product thus formed has utility as a monolithic infrared detector in which a plurality of detector elements are formed in the HgCdTe layer and a signal processing circuit is formed in the silicon substrate.

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Tokyo, Japan

Hiroji Ebe