Sandisk Technologies Inc.

Hiroaki Koketsu

Masatoshi Nishikawa

Fumiaki Toyama

Toru Miwa

Yuki Mizutani

Ryoichi Honma

Masaaki Higashitani

Johann Alsmeier

Chun-Ming Wang

Masayuki Hiroi

Takuya Futase

Masahide Matsumoto

Chenche Huang

Eiichi Fujikura

Junji Oh

Susumu Okazaki

A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices.

Passive devices for integration with three-dimensional memory devices

A switching field effect transistor and the memory devices can be formed employing a same set of processing steps. An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures for memory devices and gate dielectric-channel structures for the field effect transistor can be simultaneously formed in a memory region and in a transistor region, respectively. After replacement of the sacrificial material layers with electrically conductive layers, portions of the electrically conductive layers in a memory region are electrically isolated from one another to provide independently controlled control gate electrodes for the memory devices, while portions of the electrically conductive layers in the transistor region are electrically shorted among one another to provide a single gate electrode for the switching field effect transistor.

Field effect transistor with a multilevel gate electrode for integration with a multilevel memory device

A structure is formed on a substrate, which includes a stack of alternating layers comprising insulating layers and electrically conductive layers and a plurality of memory stack structures extending through the stack. At least one bridge line structure is formed on top surfaces of a respective subset of the plurality of memory stack structures to provide local lateral electrical connection. At least one dielectric material layer is formed over the at least one bridge line structure and the plurality of memory stack structures. A plurality contact via structures is formed through the dielectric material layer. The plurality of contact via structures includes at least one first contact via structure contacting a top surface of a respective bridge line structure, and second contact via structures contacting a top surface of a respective memory stack structure.

Bridge line structure for bit line connection in a three-dimensional semiconductor device

A NAND flash memory integrated circuit chip includes a cell area and a peripheral area with structures of different heights, with higher structures in the peripheral area to provide low resistance and lower structures in the memory array so that the risk of word line collapse is maintained at acceptable levels.

NAND flash memory integrated circuits and processes with controlled gate height

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Yokkaichi, Japan

Hiroaki Koketsu