Hitachi-high-technologies Corporation

Hitachi, Ltd.

Hiroaki Ishimura

Masamichi Sakaguchi

Go Saito

Motohiko Yoshigai

Takao Arase

Hitoshi Kobayashi

Takahiro Shimomura

Toru Ito

Ken Yoshioka

Naoyuki Kofuji

Takeshi Ohmori

Takahiro Abe

Nobuyuki Negishi

Yasuhiro Nishimori

Yoshiharu Inoue

Hayato Watanabe

Kazuo Takata

Masunori Ishihara

Toshiaki Nishida

Yutaka Kudoh

Akito Kouchi

In a process of dividing gates of multi-layered films in fabricating a NAND flash memory having a three-dimensional structure, a pattern is prevented from deforming and falling. A ratio of a length L to a height h of control gate groups configuring a memory cell of the flash memory is set to be less than 1.65 which is a range in which buckling does not occur. It is desirable that a ratio of a length L to a width W of the control gate groups is set to be less than 16.5.

Semiconductor device manufacturing method

The present invention provides a plasma processing method in which sideetching and microloading can be suppressed in a plasma processing method of forming trenches with a mask having a minimum opening width of 20 nm or less. The plasma processing method of the present invention is characterized by including the steps of forming trenches by plasma etching, forming a nitride film on sidewalls of trenches using plasma, and forming an oxide film on sidewalls and bottom surfaces of the trenches using plasma.

Plasma processing method

In the present invention, provided is a plasma processing method which reduces or eliminates the emission of contaminating matters caused by a quality-altered layer on the surface of yttria of a processing chamber's inner wall and parts inside the processing chamber. It is the plasma processing method including an etching step of setting a sample inside the processing chamber, and etching the sample, a deposition-product removing step of removing a deposition product by using a plasma, the deposition product being deposited inside the processing chamber by the etching step, the plasma being generated using a gas which contains fluorine or chlorine, and a step of exposing, to a rare-gas-based plasma, the inside of the processing chamber after the deposition-product removing step.

The invention provides a dry etching method capable of obtaining a good profile with little side etch without receiving the restriction of a micro loading effect. A dry etching method for etching a sample having formed on the surface thereof a pattern with an isolated portion and a dense portion using plasma comprises a first etching step using an etching gas containing a CF-based gas and a nitrogen gas in which an etching rate of a dense portion of the pattern is greater than the etching rate of the isolated portion of the mask pattern, and a second etching step in which the etching rate of the isolated portion of the pattern is greater than the etching rate of the dense portion of the pattern.

Dry etching method

In a plasma processing apparatus using electrostatic chuck, increase of plasma potential is prevented and abnormal discharge is avoided. The plasma processing apparatus comprises an RF source for generating plasma in a vacuum container, another RF source for applying an RF bias power to a sample, a sample stage having an electrostatic chuck electrode, a DC power supply for applying an electrostatic chuck voltage to the electrode, and a controller for shifting the electrostatic chuck voltage to negative by a potential difference of quarter to half of peak-to-peak voltage of the RF bias power for suppressing increase of plasma potential.

Plasma processing method and plasma processing apparatus

A plasma processing method is provided of processing a sample having a silicon nitride layer with high accuracy of size in anisotropy and excellent selectivity to a silicon oxide layer as underlayer. A mixed atmosphere of chlorine gas containing no fluorine with aluminum is converted into plasma in a plasma etching processing chamber and the sample having the silicon nitride layer is etched by using the plasma.

Plasma processing method for working the surface of semiconductor devices

A method for manufacturing a semiconductor device comprises etching a semiconductor substrate having an insulation film as mask using a mixed gas composed of HBr and CHF3, thereby having a reaction product composed of the semiconductor substrate and reaction gas to be adhered gradually on the side walls of the mask, and as a result creating a trench having a sufficient roundness formed to the upper end portion thereof.

Method for manufacturing semiconductor device

Growing community of inventors

Kudamatsu, Japan

Hiroaki Ishimura