Denso Corporation

Nippondenso Co., Ltd.

Hiroaki Himi

Seiji Fujino

Noriyuki Iwamori

Shigeki Takahashi

Hitoshi Yamaguchi

Masahiko Osada

Shoji Mizuno

Satoshi Shiraki

Harutsugu Fukumoto

Takashi Nakano

Masaki Matsui

Hiroyuki Kishita

Tadashi Hattori

Nobuei Ito

Hiroyuki Ban

Toshiyuki Morishita

Akira Yamada

Kazuhiro Tsuruta

Hideki Saito

Akiyoshi Asai

Masatake Nagaya

Takeshi Kuzuhara

Masatoshi Kato

Osamu Seya

Tosiaki Nisizawa

Akinari Fukaya

A semiconductor device includes a common diffusion structure formed in each region of a substrate in which semiconductor components are formed. The diffusion structures are separated into sections by trenches to form semiconductor components. The trenches define sizes of the semiconductor components and isolate the semiconductor components from the surrounding area.

Semiconductor device with trench structure

An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiOis formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.

Method for manufacturing semiconductor substrate

A semiconductor device includes insulated and separated transistor elements successively connected to one another between ground potential and a predetermined potential. A transistor element at the GND potential side is a first stage and a transistor element at the predetermined potential side is an n-th stage. Resistance elements or capacitance elements are successively connected to one another in series between the GND potential and the predetermined potential. A resistance or capacitance element at the GND potential side is a first stage and a resistance or capacitance element at the predetermined potential side is an n-th stage. Gate terminals of the transistor elements at the respective stages excluding the transistor element at the first stage are successively connected to connection points. An output is taken from the terminal at the predetermined potential side of the transistor element of the n-th stage.

Semiconductor device

Semiconductor device with trench structure and method for manufacturing the same

An NPN bipolar transistor and a PNP bipolar transistor are formed in a semiconductor substrate. The NPN bipolar transistor has a p type emitter region, a p type collector region and an n type base region and is formed in an NPN forming region. The PNP bipolar transistor has an n type emitter region, an n type collector region and a p type base region and is formed in a PNP forming region. Only one conductive type burying region is formed in at least one of the NPN forming region and the PNP forming region. A current that flows from the p type emitter region to the n type base region flows in the n type base region in a direction perpendicular to the substrate.

Semiconductor device having bipolar transistors

An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.

In an LDMOS, an n-type region which is formed to have a concentration higher than that of an n-type substrate and whose concentration gradually increases from the n-type substrate to an n type drain region is disposed so as to surround the n -type drain region Further, a p -type contact region disposed adjacent to an n -type source region is formed so as to extend below the n -type source region so that a parasitic transistor formed by the n -type source region a p-type base region and the n-type substrate is hardly turned ON.

Semiconductor device having lateral MOSFET (LDMOS)

A scan driver IC for an EL element in an EL display device supplies, in a positive field, a positive polarity scan voltage and an offset voltage which is higher than ground to scan side driver ICs from voltage supply circuits, and the scan side driver ICs set voltage of scan electrodes to be the offset voltage in the positive field, together with outputting the positive polarity scan voltage to the scan electrodes during electroluminescence timing. Consequently, a voltage of Vr-Vm is applied to the scan side driver ICs, and so the breakdown voltage can be lowered by an amount corresponding to the offset voltage Vm. Circuits for providing such voltages, for providing alternating current drive voltages, and for reducing power consumption of the drive circuits are also disclosed.

Electroluminescent display device

A high breakdown voltage semiconductor device formed in an SOI structure is disclosed. An MOS transistor composed of a drift layer, p well, a source, a gate, and a drain is formed in an island region surrounded by insulators on a semiconductor substrate. Furthermore, an electricfield-alleviating layer is formed in a bottom portion of the Si island region. The electric-field-alleviating layer is a semiconductor layer of exceeding low concentration, e.g., intrinsic, and therefore a virtual PIN structure is structured among the p well and the drift layer. Because the electric-field-alleviating layer corresponds to an I layer of the PIN structure, a depletion layer is created within the electric-field-alleviating layer when high voltage is applied to the MOS transistor, the high voltage is distributed throughout this depletion layer, and high breakdown voltage can be obtained.

Semiconductor device having a high breakdown voltage

In a dielectric isolation substrate, an end point of a polishing process for selective polishing for forming an SOI layer is detected with a high precision. When polishing a wafer with a polishing pad, the temperature of a region of the polishing pad having polished the wafer at a position immediately thereafter is detected by a temperature sensor and the selective polishing process is ended by discriminating that the rate of variation in the detected temperature has changed from a positive to a negative state and then to a fixed saturated state.

Polishing method for SOI

Electroluminescent display driver device

A semiconductor device of SOI structure exhibits a excellent heat-radiating characteristic while assuring breakdown-voltage and element-isolating performance. A buried silicon oxide film having a thickness required by the breakdown-voltage of a semiconductor element is buried between a SOI layer and a silicon substrate. A SOI layer is divided into island silicon regions by a groove for electrical-isolation use, and the groove is filled with dielectric such as an oxide film and polycrystalline silicon. In an island silicon region, a LDMOS transistor having high breakdown voltage may be formed as the semiconductor element, and potential distribution is created in accordance with a voltage application to the semiconductor element. The buried silicon oxide film at a region where low electric potential is distributed, for example a region below a grounded well region of the LDMOS transistor, is made thin. Through the thin portion of the buried silicon oxide film, heat generated by the operation of the semiconductor element can easily be propagated to the silicon substrate and radiated.

Semiconductor device having a silicon-on-insulator structure

A multi-channel type intelligent power IC which solves the problems of parasitic transistor and increase in an area of isolation region, both of which are inherent problem in a pn junction isolation substrate. The power IC also enhances heat-radiation performance. An n type first semiconductor substrate and p type second semiconductor substrate are directly bonded, and a buried oxide film is formed in a portion of a bonding interface thereof. Subsequently, a plurality of isolation trenches are formed and the first semiconductor substrate is separated into an SOI isolation region and a pn isolation region. Logic elements are then formed in the SOI isolation region, and power elements are formed in the pn isolation region. In the case wherein two or more logic elements are hereby formed, the logic elements are isolated by isolation trenches. In the case wherein two or more power elements are formed, a parasitic current extracting portion is formed between mutual power elements.

Growing community of inventors

Nagoya, Japan

Hiroaki Himi