Intel Corporation

Xilinx, Inc.

Hing Yan To

James A McCall

Joseph H Salmon

Mamun Ur Rashid

Joe Salmon

Aaron K Martin

Michael W Leddige

Jonathan H Liu

Roger K Cheng

Martin L Voogel

Jahanshir J Javanifard

Michael W Williams

Navneet Dour

Harishankar Sridharan

Jen-Tai Hsu

Yanran Chen

Edward C Priest

Michael Sandhinti

Maria George

John J Rinck

Michelle Y Eng

Xi Long

Juan Wang

A semiconductor device comprises a printed circuit board (PCB), a plurality of vias, and a communication buss. The PCB comprises a plurality of layers. The first layer of the plurality of layers is configured to receive a first integrated circuit (IC) device and a second IC device. The plurality of vias is disposed within the plurality of layers. A first via of the plurality of vias is configured to be connected to the first IC device, and a second via of the plurality of vias is configured to be connected to the second IC device. The communication bus comprises a first trace connected to the first via. The communication device further comprises a second trace disposed on a third layer of the plurality of layers and connected to the first via. The first trace is disposed on a layer of the plurality of layers other than the second layer.

Routing a communication bus within multiple layers of a printed circuit board

Some examples described herein provide for an on-die virtual probe in an integrated circuit structure for measurement of voltages. In an example, an integrated circuit comprises a voltage-controlled frequency oscillator circuitry and a processor circuitry. The voltage-controlled frequency oscillator circuitry comprises a plurality of circuitry components and is configured to generate a signal having a frequency related to a supply voltage. The voltage-controlled frequency oscillator circuitry is disposed at a location of the integrated circuit proximal to the supply voltage being monitored. The processor circuitry is configured to identify a relationship between the frequency of the signal and the supply voltage. The processor circuitry is also configured to determine a value of the supply voltage associated with the signal based on the identified relationship. The processor circuitry further monitors on-die transient voltages at the location of the integrated circuit based on the value of the supply voltage.

On-die virtual probes (ODVP) for integrated circuitries

Some examples described herein relate to a design system and a method for printed circuit board (PCB) design. In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to provide a workspace in a user interface in which a PCB design comprising multiple layers is capable of being created; provide a list of layout templates in the user interface; and provide an insert function, via the user interface, configured to insert a selected layout template of the list of layout templates into the workspace to be included in the PCB design. Each layout template of the list of layout templates is a tile layout that includes a layout component and metal lines that extend to one or more edges of the tile layout.

Printed circuit board (PCB) modular design

De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.

Nibble de-skew method, apparatus, and system

A technique includes providing transmitters that are each associated with a data bit line of a bus, and each transmitter is clocked by an associated transmit clock signal. The technique includes determining a baseline offset to apply to a base clock signal to synchronize the base clock signal to a source clock signal of a source that supplies data to the transmitters. For each transmitter, an associated phase offset is determined to compensate for an associated skew. The phase of each transmit clock signal is controlled based on the associated phase offset and the baseline offset.

Clock synchronization scheme for deskewing operations in a data interface

A method and device are disclosed. In one embodiment the method includes driving a first clock domain reference signal on a first clock tree and driving a second clock domain reference signal on a second clock tree. The first tree routes the first signal from a PLL to a first clock domain drop off circuit and the second tree routes the second signal from the PLL to a second clock domain drop off circuit. A jitter produced from the second tree is less than a jitter produced from the first tree. The method continues by detecting any phase misalignment between the first signal and the second signal. The method also causes the first signal to be delayed so that it aligns with the second signal.

Dual-path clocking architecture

An embodiment of the present invention is a technique to calibrate an integrating receiver. A delay calibration circuit calibrates an adjusting code of a chain of delay elements and positioning of at least an integrating strobe used to define an integration window for the integrating receiver. An integrating receiver pulse generator generates an IR pulse from the at least integrating strobe. A calibration controller controls calibrating the adjusting code and the positioning of the at least integrating strobe.

Calibrating integrating receivers for source synchronous protocol

Transmission of digital signals across a bus between an electronic device having a transmitter and another electronic device having a receiver with termination for both the transmitter and receiver being referenced to ground, such that the electronic device having the transmitter and the other electronic device having the receiver are able to be powered with differing decoupled voltages, such that the voltage employed by the electronic device having the transmitter is able to be lower than the voltage employed by the other electronic device having the receiver, and wherein the electronic device having the transmitter may transmit addresses and/or commands to the other device having the receiver using single-ended signaling, while both electronic devices may exchange data using differential signaling.

Method and apparatus for power efficient and scalable memory interface

A method and system for a configurable Vcc reference and Vss reference differential current mode transmitter is described. The system includes a Vss reference differential current mode driver, a Vcc reference differential current mode driver coupled to the Vss reference current mode driver, and a controller circuit coupled to the Vss reference differential current mode driver and the Vcc reference differential current mode driver to select between the Vss reference differential current mode driver and the Vcc reference differential current mode driver based on a type of transmission interface.

Method and system for a configurable Vcc reference and Vss reference differential current mode transmitter

According to one embodiment, a memory controller is disclosed. The memory controller includes a phase locked loop (PLL) to generate a differential reference clock and a first clocking component coupled to the PLL. The first clocking component includes a first delay locked loop (DLL) to receive the reference clock and to generate transmit and receive delay de-skew clock signals, a first set of phase interpolators to provide data transmit de-skewing and a first set of slave delay lines to provide data receive de-skewing.

Modular memory controller clocking architecture

The invention includes a method to adjust integrated circuit device I/O bus timing. In one embodiment, the method includes comparing an alignment between an edge of a first clock signal to a center of a data packet to produce an alignment offset signal and adjusting the first clock signal using a variable delay device in response to the alignment offset signal to substantially align the edge of the first clock signal to the center of the data packet. Other embodiments are claimed and described.

Optimization of integrated circuit device I/O bus timing

A method, apparatus, and system are disclosed. In one embodiment the method comprises inputting an early clock signal and a late clock signal to a memory device and generating an average clock signal for the memory device by averaging the early clock signal and the late clock signal.

Latency normalization by balancing early and late clocks

Methods and devices for calibrating a driver on a slave device, using a master device driver as a load, are disclosed. A master reference driver is integrated on the same circuit as the master device driver, with both drivers having the same layout and geometry. The master reference driver is calibrated using a selected load impedance that includes the nominal slave device driver impedance and any other impedance elements. The same calibrated driver setting is concurrently applied to both the master driver and the master reference driver, while the slave device drives the master driver. The voltage at the master driver is compared to the voltage at the master reference driver, and the slave device driver impedance is adjusted until those voltages match. The resulting calibration of the slave device driver impedance is largely independent of the actual impedance of the master device driver.

Growing community of inventors

Folsom, CA, United States of America

Hing Yan To