Tdk Corporation

Hideyuki Seike

Makoto Orikasa

Yuhei Horikawa

Hisayuki Abe

Kenichi Yoshida

Shin Fujita

A method for producing a semiconductor chip is a method for producing a semiconductor chip that includes a substrate, a conductive portion formed on the substrate, and a microbump formed on the conductive portion, which includes a smooth surface formation process of forming a smooth surface on the microbump, and the smooth surface formation process includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump and among principal surfaces of the pressure application member, a principal surface that contacts the microbump is a flat surface.

Method for producing semiconductor chip

A method for producing a semiconductor package is a method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on the substrate, and microbumps formed on the conductive portions, are laminated, which includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump.

Method for producing semiconductor package

A method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on the substrate, and microbumps formed on the conductive portions, are laminated, which includes a smooth surface formation process of forming a smooth surface on the microbump, a lamination process of laminating three or more of the semiconductor chips by overlaying the microbump of one of the semiconductor chips on the microbump of another one of the semiconductor chips, and a bonding process of bonding the semiconductor chips to each other via the microbumps by heating to melt the microbumps, in which in the lamination process, of one of the semiconductor chips and another one of the semiconductor chips, the smooth surface is formed on at least one of the microbump, and one of the microbump contacts another one of the microbump on the smooth surface.

The present invention relates to a terminal structure comprising; a base material; an external electrodeformed on the base material; an insulating coating layerformed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under-bump metal layerfilling the opening and covering part of the insulating coating layer; and a dome-shaped bumpcovering the under-bump metal layer, wherein in a cross section along a lamination direction, the under-bump metal layer has a convex shape toward the bump, and the thickness Tof the under-bump metal layer at a center of the opening is equal to or greater than the thickness Tof the under-bump metal layer at an end portion of the opening.

Terminal structure and semiconductor device

A preferred terminal structure comprises a base material; an electrode formed on the base material; an insulating covering layer formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under bump metal layer containing Ni, formed in a region in the opening on the electrode so that an upper surface of the metal layer is at a position lower than an upper surface of the insulating covering layer in a peripheral edge portion of the opening; and a dome-shaped bump containing Sn and Ti, formed in a region in the opening on the under bump metal layer, wherein an end portion of a boundary between the under bump metal layer and the bump is in contact with an inner wall of the opening portion in the insulating covering layer.

Terminal structure, and semiconductor element and module substrate comprising the same

A coating for a conductor, the coating having a layered structure of a palladium layer. The palladium layer has a crystal plane whose orientation rate is 65% or more, which means 65% or more of the crystal planes of the palladium layer are aligned to this crystal plane. Preferably the crystal plane whose orientation rate is 65% or more in the coating is the (111) plane or (200) plane.

Coating and electronic component

The present invention relates to a terminal structure comprising: a base material; an external electrodeformed on the base material; an insulating coating layerformed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under-bump metal layerfilling the opening and covering part of the insulating coating layer; and a dome-shaped bumpcovering the under-bump metal layer, wherein in a cross section along a lamination direction, a height Hat which the bump has a maximum diameter (L) is lower than a maximum height Hof the under-bump metal layer.

A preferred terminal structure comprises a base material; an electrode formed on the base material; an insulating covering layer formed on the base material and on the electrode and having an opening exposing at least part of the electrode; an under bump metal layer containing Ni, filling the opening on the electrode; and a dome-shaped bump containing Sn and Ti, covering the under bump metal layer, wherein at least part of the under bump metal layer has a portion sandwiched between the external electrode and the insulating covering layer.

A coating having a layered structure including a palladium layer is provided to a conductor. The highly stable palladium layer is amorphous and contains phosphorus in a concentration ranging from 7.3% by mass to 11.0% by mass. An electronic component may include the conductor coated with the coating. The conductor coated with the coating has superior corrosion resistance and superior reliability in electrical connection with external apparatuses.

The electronic device includes a terminal structure and a printed circuit board including the terminal structure. The terminal structure includes a solder-joint conductor region placed on a wiring conductor, an intermediate layer contacting with the conductor region, and a solder region contacting with the intermediate layer. The intermediate layer includes an intermetallic compound including tin and at least one of copper and nickel as principal components. When the indentation elastic modulus of the conductor region is Eand the indentation elastic modulus of the intermediate layer is E, the ratio of Eto Eis equal to or more than 0.8 and equal to or less than 1.5.

Growing community of inventors

Tokyo, Japan

Hideyuki Seike