Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Renesas Technology Corp.

Hitachi Ulsi Engineering Corp.

Hitachi Hokkai Semiconductor Ltd.

Hidetomo Aoyagi

Yoshihisa Koyama

Masaya Muranaka

Hiroyuki Uchiyama

Ryoichi Hori

Yasushi Takahashi

Kazuyuki Miyazawa

Masamichi Ishihara

Hisashi Nakamura

Hidetoshi Iwai

Satoshi Oguchi

Hiromi Matsuura

Shigetoshi Sakomura

Haruo Ii

Takeshi Kizaki

Makoto Morino

Sinichi Miyatake

Toshitugu Takekuma

Kazumasa Yanagisawa

Toshio Yamada

Shoji Kubono

Hiroshi Yoshioka

Yukihide Suzuki

Shinji Udo

Manabu Tsunozaki

Shoji Wada

Masahiro Ogata

Kanehide Kenmizaki

Yoshihiro Shinozaki

Kyoko Ishii

Tetsuya Kitame

Masahiro Katayama

Nobuhiko Ohno

Koichi Nozaki

Akihiko Hoshida

Seiichi Shundo

Toshitugu Takemuma

Outside-cell wiring that extends the upper part of a macro cell to the direction of X axis is composed of the wiring layer of the upper layer than a terminal for a signal of the macro cell and this terminal is formed to extend in the direction of Y axis (direction that intersects the direction of X axis) so that the outside-cell wiring can be secured for a plurality of wiring channels. The macro cell and the outside-cell wiring are connected via this signal terminal.

Semiconductor device, a method of manufacturing the same and storage media

A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

Semiconductor memory device with improved substrate arrangement to

A defect remedy LSI mounted on a memory module, comprising: an input interface portion for capturing address and control signals, the input interface portion being the same as that of a dynamic RAM; an input/output interface portion corresponding to a data bus of a memory device comprised of a plurality of dynamic random access memories; a memory circuit to which a chip address and an X defective address of any of the plurality of random access memories are electrically written, the memory circuit being substantially made nonvolatile; a redundancy remedy RAM portion composed of a static RAM wherein a word line is selected by a compare match signal between an X address signal and the defective address of the memory circuit, the X address signal and the defective address being captured via the input interface portion, and a column is selected by a Y address signal captured via the input interface portion; a selecting portion for connecting a data input/output bus of the redundancy remedy RAM portion to an input/output circuit corresponding to a defective chip address; a data input/output portion for selectively activating an input/output circuit to be connected to a data bus corresponding to a dynamic RAM found defective; and a mask portion for outputting a control signal for putting in a high-impedance state an output pin of the defective RAM in a read operation.

Semiconductor memory system

A semiconductor integrated circuit device constituted by a plurality of sets each of which having a pair of memory mats and each memory mat having a plurality of memory cells arranged in a matrix and a sense amplifier, I/O lines for transmitting signals provided by the sense amplifiers, selecting circuitry for selecting either a condition for sending out the signals provided by the sense amplifiers on the I/O lines or a condition for not sending out the same on the I/O lines, and Y-selection lines for transmitting the selection signals. A decoder connected with selection is disposed substantially at the middle of the Y-selection lines. X- and Y-address buffers are disposed close to each other nearer to the center of the chip than X- and Y-redundant circuits. A reference voltage generating circuit is disposed nearer to the edge of the chip than an output buffer circuit. A relief selecting circuit of each memory mat is formed adjacent to a redundant line selecting circuits included in the same memory mat. At least some of wiring lines connected to each sense amplifier are formed in a wiring layer in which Y-selection lines are formed. The Y-selection lines are extended in gaps between the sense amplifiers.

Semiconductor integrated circuit device

Growing community of inventors

Akishima, Japan

Hidetomo Aoyagi