Tokyo Electron Limited

Hideto Goto

Takayuki Niuya

Michihiro Ono

Yoshinori Marumo

Kyungho Park

Katsusuke Shimizu

The present invention is directed to suppressing the rise of a dielectric constant of insulating film during a procedure of burying wiring in semiconductor devices by using a damascene process, and it is also directed to simplifying a process of manufacturing the semiconductor devices. In terms of a process step of forming protection film on a metal layer during the damascene process, there is employed a combined arrangement of a wash unit where particles are removed from polished substrates with a processing unit where a solution containing an organic substance such as benzotriazole, which tends to be bound to the metal layers, is applied to the metal layers over the substrates after the particles are removed therefrom. For the combined arrangement of the processing unit and the wash unit, either a batch processing unit or a mono/serial processing unit can be employed.

Method of manufacturing semiconductor device and manufacturing apparatus

The object of the present invention is to provide a plating method capable of planarization process of high quality in comparison with the conventional plating method and also provide a plating device and a plating system adopting the plating method of the invention. In the plating method and device, an object to be processed and an electrode plate are dipped in a solution including objective metal ions and a forward current is supplied between the object and the electrode plate to educe a metal on the surface of the object. After forming a plating film on the object excessively, a backward current is supplied between the object and the electrode to uniformly remove at least part of superfluous plating film.

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Tsukuba, Japan

Hideto Goto