Nec Corporation

Renesas Electronics Corporation

Nec Electronics Corporation

Hidetaka Natsume

Satoshi Yamamoto

Hitoshi Mitani

Takami Hiruma

Nolifumi Sato

Kiyokazu Hashimoto

Toshikatsu Jinbo

Hiroshi Furuta

Kenji Hibino

Shinji Ohara

Toshifumi Takahashi

Hiroyuki Hoshizaki

Norifumi Sato

A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits.

Semiconductor integrated circuit with thick gate oxide word line driving circuit

Semiconductor integrated circuit

A semiconductor device in which a conductor of a bit line may be made as large in thickness as possible to reduce resistance of the bit line and to reduce capacitance across the neighboring bit lines. The device includes a first interlayer film having a first contact metal part accommodated in it, and a second interlayer film. The second interlayer film includes a trench, and is deposited on the first interlayer film. The semiconductor device also includes a metal conductor filled in and protruding above the trench, and a hard mask film deposited on the metal conductor. The semiconductor device also includes sidewalls formed on lateral surfaces of the hard mask film and the metal conductor for overlying the second interlayer film, and a third interlayer film formed above the second interlayer film inclusive of the hard mask film and the sidewalls. The device also includes a contact hole opened through the third interlayer film and the second interlayer film and in the first interlayer film to expose the first contact metal part between the sidewalls. The device further includes a second contact metal partin the contact hole.

Method for manufacturing semiconductor device and semiconductor device

Semiconductor integrated circuit having DRAM word line drivers

A conventional layout of power supply protective element cannot sufficiently protect an internal circuit against a surge current that flows into a narrow branch line that branches off from a thick main wiring line. A semiconductor device according to an embodiment of the present invention includes a power supply protective element connected around a terminal; a main wiring line connected with a VCC pad or a GND pad; a branch line that branches off from the main wiring line and applies a power supply potential or a ground potential to a functional block of the semiconductor device; a branching portion at which the branch line branches off from the main wiring line; and an internal power supply protective element connected with the branch line.

Semiconductor device

A semiconductor memory device includes first and second source/drain regions, and first and second semiconductor regions. The first source/drain region of a first conductive type is formed in a first well region of a second conductive type for a pair of first MIS-type transistors of the first conductive type. The second source/drain region of the second conductive type is formed in a second well region of the first conductive type for a pair of second MIS-type transistors of the second conductive type. The first semiconductor region of the second conductive type is formed in the first source/drain region. The second semiconductor region of the first conductive type is formed in the second source/drain region.

Semiconductor memory device with plural source/drain regions

The present invention relates to a semiconductor memory device having a SRAM in which a memory cell comprises a pair of transmission transistors and a flip-flop circuit containing a pair of driver transistors and a pair of load transistors, wherein: a first conductive film interconnection formed from a first conductive film which is set on a semiconductor substrate, constitutes respective gate electrodes of said driver transistors, load transistors and transmission transistors; an inlaid interconnection set in a first insulating film lying on said semiconductor substrate, constitutes one of a pair of local interconnections cross-coupling a pair of input/output terminals in said flip-flop circuit; and a second conductive film interconnection formed from a second conductive film which is set on a second insulating film lying on said first insulating film, constitutes the other one of said pair of local interconnections. The present invention can provide a SRAM whose memory cell size is readily reduced without unduly increasing the number of the steps in the manufacturing method thereof. Further, the present invention can improve the &#x3b1;-ray soft error resistance of the SRAM.

Semiconductor memory device and manufacturing method thereof

The present invention relates to a semiconductor memory device having a SRAM in which a memory cell comprises a pair of transmission transistors and a flip-flop circuit containing a pair of driver transistors and a pair of load transistors, wherein: a first conductive film interconnection formed from a first conductive film which is set on a semiconductor substrate, constitutes respective gate electrodes of said driver transistors, load transistors and transmission transistors; an inlaid interconnection set in a first insulating film lying on said semiconductor substrate, constitutes one of a pair of local interconnections cross-coupling a pair of input/output terminals in said flip-flop circuit; and a second conductive film interconnection formed from a second conductive film which is set on a second insulating film lying on said first insulating film, constitutes the other one of said pair of local interconnections.

A semiconductor device has a gate electrode which is formed on a first conductive-type well set in semiconductor substrate, with a gate insulating film lying therebetween; a LDD structure in which, on either side of said gate electrode, there are formed a LDD region and a source/drain region; an interlayer insulating film to cover said gate electrode as well as said LDD regions; and contact sections. A contact section connecting to one side of the source/drain regions having a potential equal to a potential of said first conductive-type well is disposed so as to come into contact with the LDD region lying thereunder; and a contact section connecting to the other side of the source/drain region having a potential different from the potential of said first conductive-type well is disposed so as not to come into contact with the LDD region lying thereunder. The present invention can develop technology capable to reduce the memory cell area while suppressing the generation of the leakage, and provide a semiconductor memory device of high integration with excellent element characteristics having a low standby current.

In a semiconductor device including a semiconductor substrate, a well formed on the semiconductor substrate, and a thick field insulating layer for surrounding an active area of the well, a contact structure is buried in a contact hole provided in the thick field insulating layer and connected to the well, so as to fix a voltage at the well.

Semiconductor device capable of surely fixing voltage at well

An SRAM cell is arranged in a semiconductor device. A metal oxide semiconductor field effect transistor is arranged in the SRAM cell. An interlayer insulating film is formed on the metal oxide semiconductor field effect transistor. A load resistor conductive layer is formed on the interlayer insulating film. In addition, a wiring conductive layer which connects the gate electrode of the metal oxide semiconductor field effect transistor to the load resistor conductive layer is provided. The resistance of the wiring conductive layer is lower than the resistance of the load resistor conductive layer. A side wall is formed between the load resistor conductive layer and the wiring conductive layer.

Semiconductor device and method of manufacturing the same

The upper surface of a field oxide film 102 is made planar to eliminate a swell normally formed. More specifically, the field oxide film 102 is formed by recess LOCOS method so as to be convex formed in the direction toward the inside of a substrate 101 while having an upper surface that is substantially planar.

Semiconductor device having field isolating film of which upper surface is flat and method thereof

A semiconductor device having a semiconductor substrate, an impurity diffused layer formed in a principal surface of the semiconductor substrate, a conductive member formed on the semiconductor substrate adjacent to the impurity diffused layer and having a sloped surface inclined to the principal surface of the semiconductor substrate, an insulator film deposited to cover the impurity diffused layer and the conductive member, and a common contact hole formed through the insulator film to extend over a surface of the impurity diffused layer and the sloped surface of the conductive member.

Growing community of inventors

Kanagawa, Japan

Hidetaka Natsume