Sumitomo Mitsubishi Silicon Corporation

Sumitomo Metal Industries, Inc.

Sumitomo Sitix Corporation

Hideshi Nishikawa

Toshiaki Ono

Nobumitsu Takase

Tadami Tanaka

Eiichi Asayama

Masataka Horai

Makoto Ito

Shinsuke Sadamitsu

Shigeru Umeno

Yasuo Koike

Hiroshi Hayakawa

Kazuyuki Egashira

Masakazu Sano

Naoshi Adachi

Koji Sueoka

Koujl Sueoka

A high-resistance silicon wafer is manufactured in which a gettering ability, mechanical strength, and economical efficiency are excellent and an oxygen thermal donor is effectively prevented from being generated in a heat treatment for forming a circuit, which is implemented on the side of a device maker. A heat treatment for forming an oxygen precipitate nucleus is performed at 500 to 900&#xb0; C. for 5 hours or more in a non-oxidizing atmosphere and a heat treatment for growing an oxygen precipitate is performed at 950 to 1050&#xb0; C. for 10 hours or more on a high-oxygen and carbon-doped high-resistance silicon wafer in which resistivity is 100 &#x3a9;cm or more, an oxygen concentration is 14&#xd7;10atoms/cm(ASTM F-121, 1979) or more and a carbon concentration is 0.5&#xd7;10atoms/cmor more. By these heat treatments, a remaining oxygen concentration in the wafer is controlled to be 12&#xd7;10atoms/cm(ASTM F-121, 1979) or less. Thus, there is provided a high-resistance, low-oxygen and high-strength silicon wafer in which resistivity is 100 &#x3a9;cm or more and an oxygen precipitate (BMD) having a size of 0.2 &#x3bc;m is formed so as to have high density of 1&#xd7;10/cmor more.

High resistance silicon wafer and its manufacturing method

A silicon annealed wafer having a sufficient thick layer free from COP defects on the surface, and a sufficient uniform BMD density in the inside can be produced by annealing either a base material wafer having nitrogen at a concentration of less than 1&#xd7;10atoms/cm, COP defects having a size of 0.1 &#x3bc;m or less in the highest frequency of occurrence and no COP defects having a size of 0.2 &#x3bc;m or more, oxygen precipitates at a density of 1&#xd7;10counts/cmor more, and BMDs (oxygen precipitates), where the ratio of the maximum to the minimum of the BMD density in the radial direction of the wafer is 3 or less, or a base material wafer grown at specific average temperature gradients within specific temperature ranges and specific cooling times for a single crystal at a nitrogen concentration of less than 1&#xd7;10atoms/cm, employing the Czochralski method. Moreover, a silicon epitaxial wafer having very small defects and a uniform BMD distribution in the inside can be formed by growing an epitaxial layer on the surface of either the first type base material wafer or the second type base material wafer. Both the silicon annealed wafer and the silicon epitaxial wafer greatly reduce the rate of producing defective devices, thereby enabling the device productivity to be enhanced.

Silicon annealed wafer and silicon epitaxial wafer

To suppress a fluctuation in resistivity around a target value to thereby stably manufacture high resistivity silicon single crystals having almost the same resistivity values in a manufacturing method wherein a silicon raw material is molten to manufacture a high resistivity silicon single crystal in the range of from 100 to 2000 &#x3a9; cm with a CZ method. In a case where poly-silicon produced with a Siemens method using trichlorosilane as raw material is used as the silicon raw material, an impurity concentration in the silicon raw material is selected so as to be controlled in the range of from &#x2212;5 to 50 ppta method in terms of (a donor concentration&#x2014;an acceptor concentration) and the selected poly-silicon is used. In a case of a MCZ method, the poly-silicon is selected in the range of from &#x2212;25 to 20 ppta and the selected poly-silicon is used. Instead of the raw material, poly-silicon produced with a Siemens method using monosilane as raw material is used. Alternatively, a silicon crystal manufactured with a CZ method or a MCZ method using poly-silicon raw material is used.

Manufacturing method of high resistivity silicon single crystal

A method for growing a silicon single crystal used for semiconductor integrated circuit devices, wherein the single crystal is grown by the CZ method at a nitrogen concentration of 1&#xd7;10atoms/cm&#x2013;1&#xd7;10atoms/cmwith a cooling rate of not less than 2.5&#xb0; C./min at a crystal temperature of 1150&#xb0; C.&#x2013;1000&#xb0; C., in which case, the pulling rate is adjusted such that the outside diameter of a circular region including oxidation-induced stacking faults generated at the center of a wafer which is subjected to the oxidation heat treatment at high temperature is not more than &#x2157; of the wafer diameter, wherein the wafer is prepared by slicing the grown single crystal. In the growth method, the concentration of oxygen in the silicon single crystal is preferably not more than 9&#xd7;10atoms/cm(ASTM '79). With this method, the silicon single crystal, in which the generation of Grown-in defects can be effectively suppressed, can be produced in a simple process without any increase in the production cost. Moreover, a specification of the oxygen concentration and the application of the outward diffusion treatment are capable of producing a wafer, which is optimally used for monitoring particles.

Method for growing silicon single crystal

Epitaxial wafers showing marked IG effects can be manufactured from silicon single crystals doped or not doped with nitrogen without requiring any additional heat treatment process step while reducing the density of epitaxial layer defects. According to the first manufacturing method, an epitaxial layer is allowed to grow on the surface of a wafer sliced from a single crystal produced by employing a cooling rate of not less than 7.3&deg; C./min in the temperature range of 1200-1050&deg; C. in the step of pulling up thereof. According to the second manufacturing method, an epitaxial layer is allowed to grow on the surface of a silicon wafer sliced from a silicon single crystal doped with 1&times;10 atoms/cm to 1&times;10 atoms/cm as produced by employing a cooling rate of not less than 2.7&deg; C./min in the temperature range of 1150-1020&deg; C. and then a cooling rate of not more than 1.2&deg; C./min in the temperature range of 1000-850&deg; C. in the step of pulling up thereof.

Method of manufacturing epitaxial wafer and method of producing single crystal as material therefor

The invention relates to a method of producing epitaxial wafers for the manufacture of high integration density devices capable of showing stable gettering effect. Specifically, it provides (1) a method of producing epitaxial wafers which comprises subjecting a silicon wafer sliced from a single crystal ingot grown by doping with not less than 1&times;10 atoms/cm of nitrogen to 15 minutes to 4 hours of heat treatment at a temperature not lower than 700&deg; C. but lower than 900&deg; C. and then to epitaxial growth treatment. It is desirable that the above single crystal ingot have an oxygen concentration of not less than 11&times;10 atoms/cm . Further, (2) the above heat treatment is desirably carried out prior to the step of mirror polishing of silicon wafers. Furthermore, (3) it is desirable that the pulling rate be not increased in starting tail formation as compared with the pulling rate of the body in growing the above single crystal ingot. By taking these means, it is possible to produce epitaxial wafers having an almost constant, high level of gettering effect irrespective of the site of wafer slicing from the single crystal ingot and, furthermore, suppress the occurrence of defects within the epitaxial layer.

Method of producing epitaxial wafers

A method of manufacturing a silicon single crystal to be grown by the Czochralski method, wherein a crystal is pulled up in a CZ furnace by changing an average pulling rate for a crystal, having a predetermined length, a plurality of times, a relation between the average pulling rate and the OSF ring diameter for each pulling length is examined, an average pulling rate pattern for generation or disappearance of an OSF ring at a predetermined position is designed based on the examined results, and the single crystal is grown according to the average pulling rate pattern, and a silicon wafer not having grown-in defects is manufactured.

Growing community of inventors

Tokyo, Japan

Hideshi Nishikawa