Nec Electronics Corporation

Nec Corporation

Elpida Memory, Inc.

Elpidia Memory, Inc.

Hideo Inaba

Atsushi Nakagawa

Satoshi Yamamoto

Hiroyuki Takahashi

Masatoshi Sonoda

Takuya Hirota

Masahiro Yoshida

Noriaki Komatsu

Yoshiyuki Katou

Yoshiyuki Kato

Susumu Takano

Tadashi Onodera

Takashi Kusakari

Shouzou Uchida

Syouzou Uchida

Yuuji Torige

A semiconductor memory device is operable in normal and test operation modes. At the test operation, in response to a first active command, a row address signal that is input from the outside is captured in the row decoder, and in response to a first write/read command, a column address signal input from the outside is captured in the column decoder. At this time, a word line and a bit line are not selected. Thereafter, in response to a second active command, a word line corresponding to the row address signal is selected in the row decoder, and, in response to a second write/read command, a bit line that corresponds to the column address signal is selected in the column decoder. The time period from the time at which the second read/write command is input to the time at which the second active command is input, is measured as tRCD.

Precise tRCD measurement in a semiconductor memory device

A semiconductor device includes: first and second input/output terminals; a first input/output line connected to the first input/output terminal; a second input/output line connected to the second input/output terminal; and a first by-path route that connects the first input/output line and the second input/output line. When in normal operation mode, the first by-path route is set in a non-conductive state. When in a test mode, the first by-path route is set into a conductive state so that a first data inputted to the first input/output terminal is outputted as a first data to the second input/output line, in correspondence with a transition of a clock signal in the first direction, and so that a second data inputted to said first input/output terminal is outputted as a second input data for said first input/output line, in correspondence with a transition of said clock signal in the second direction.

Semiconductor device testable on quality of multiple memory cells in parallel and testing method of the same

High-speed operation is achieved without increase in a circuit current and unstable operation of data strobe signal level due to collision between data strobe signals. Each of RAMsandoutputs a data signal DQ and a data strobe signal DQS indicative of an output timing of the data signal. RAMincludes a strobe signal control unitthat determines whether RAMconnected in parallel with the RAMis in a read state or not, and delays an output start timing of data strobe signal DQS when the RAMis in the read state. Strobe signal control unitof the RAMcontrols output start timing so that a latter half portion of a preamble period of the data strobe signal DQS to be output coincides with a postamble period of the data strobe signal DQS output by the RAM

Semiconductor device and semiconductor chips outputting a data strobe signal

A test method and a test circuit which enable operations to be checked when the time interval between a refresh operation and a read or write operation is forcibly reduced. Timings for a read or write operation in a normal operation mode and in a test mode are determined on the basis of an address transition detection circuit. A timing for a refresh operation in the normal operation mode is set on the basis of a normal refreshing pulse signal generated by a refresh pulse generating circuit in response to a timing signal generated by a timer circuit. A timing for a refresh operation in the test mode is set on the basis of a first testing refresh pulse generation signal generated by a first testing refresh pulse generating circuit in response to the address transition detection signal. By controlling a timing for generating the first testing refresh pulse generation signal, it is possible to generate a read or write operation and a refresh operation so that there is a predetermined time interval between these operations.

Semiconductor storage device, test method therefor, and test circuit therefor

A semiconductor memory device is provided which effectively reduces a consumption of current of a system of circuits associated with refresh operations. A control signal circuitcontrols n-channel transistorsC,B to be in an OFF-state based on an internal chip select signal SCI in an interval time period between the refresh operations, wherein the n-channel transistorsC,B are connected between the system of circuits associated with refresh operations (an internal voltage-down circuitand a boost circuit) and the ground, so as to break down a leak path of the system of circuits associated with refresh operations for reducing the leakage of current. At a timing of starting the refresh operation by triggering a timer, the internal chip select signal SCI is transitioned to a high level for supplying a ground voltage to the internal voltage-down circuitand the boost circuit

Semiconductor memory device

A semiconductor memory device is provided for preventing a late-write from disturbing a refresh operation and also for reducing a current consumption in a write cycle with execution of the late-write. Upon a transition of an address ADD, an address transition detector circuit detects this address transition. Upon receipt of a result of detection by the address transition detector circuit, a state control circuit judges an operation to be executed, from an output enable signal /OE and a write enable signal /WE, and then outputs any of a read statement RS, a write statement WS, and a refresh statement FS. According to a clock signal ACLK, input signals such as addresses are taken for executions of operations based on the statements.

Semiconductor memory device for preventing a late write from disturbing a refresh operation

The present invention provides a non-synchronous semiconductor memory device configured as a pseudo-SRAM and capable of relaxing the limitation to address skew and improving the read rate. A data latch circuitholds data having been read out of memory cells in a memory cell arraydesignated by a tow address included in an address ADD in a read mode. Upon transitions of column addresses A, Aincluded in the address, a multiplexersequentially and non-synchronously feeds out the data held in the data latch circuitbased on the column addresses A, A

Non-synchronous semiconductor memory device having page mode read/write

The present invention provides a semiconductor memory device capable of checking operation in the worst case in address combinations, and its manufacturing method. Specific data for test are written into a memory cell arrayThen, a test signal TEis set '1' to set a device in a test mode. Refresh addresses for test are then stored in a data store circuitA first address for test is applied to an address terminalwhereby a normal read or write operation is accomplished based on the first address for test. A second address for test is applied to the address terminal, whereby a refresh operation is accomplished based on the address for test, and subsequently another normal read or write operation is accomplished based on the second address for test. Data of the memory cell arrayare checked to decide the presence or absence of any abnormality.

Semiconductor memory device and its test method as well as test circuit

Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/Fis set by a one shot pulse from an OS circuit, a memory access request is inputted to a memory accessing pulse generator circuitthrough a NOR gate, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gateduring the memory access, the output of the NOR gateis at the 'L' level, and the refresh request is blocked by the AND gate. Thereafter, at the time when the latch control signal LC is turned into the 'L' level, F/Fsandare reset, the output of the NOR gateis turned into the &#x201c;H&#x201d; level, the refresh request is inputted to a refreshing pulse generator circuit, and a refresh enable signal RERF is outputted.

Semiconductor storage device and refresh control method thereof

A semiconductor memory device is provided, which is capable of effectively reducing a current comsumption caused by a self-refresh operation in a stand-by mode. In the refresh operation in the stand-by mode, under the control by a refresh control circuitB, firstly, a suppression is made for current driving abilities of sense amplifiersA&#x2dc;D provided for amplifying data signals appearing on bit lines, and secondly, an expansion is made of a pulse width of a row enable signal RE, which defines a period of time for selecting word lines WL, and thirdly, parallel activations of plural word lines are made based on the row enable signal RE with the expanded pulse width, thereby reducing the frequency of operations of the circuit system associated with the refresh operations, resulting in a suppression of the current consumption.

A semiconductor memory device capable of a further reduction in power consumption for refresh operation is provided. Cell arrays S, Sare divided into respective four blocks B&#x2dc;Band B&#x2dc;B. In a normal read/write operation, by address data designating a word line, one of the cell arrays is selected, and also one block is selected in the selected cell array, and further one word line is selected in the selected block. In a refresh operation, one of the cell arrays is selected, and four blocks in the selected cell array are simultaneously refreshed. Namely, respective one word line is selected from each of the four blocks, and the selected word lines are refreshed, thereby to reduce a power comsumption as compared to when the plural cell arrays are refreshed.

Semiconductor storage and its refreshing method

A semiconductor memory device is provided which operates according to the specification of an SRAM, and which is capable of making the memory cycle shorter than heretofore, without normal access being delayed by the influence of refresh. An ATD circuit () receives change of an address ('Address'), and generates a one shot pulse in an address transition detect signal (ATD) after an address skew period has elapsed. In the case of a write request, a write enable signal (/WE) is dropped within the address skew period. First, writing or reading is performed from the rising edge of the one shot pulse, and, in the case of writing, late writing is performed using the address and the data which were presented at the time of the directly preceding write request. Next, refresh is performed during the period from the falling edge of the one shot pulse until the address skew period of the subsequent memory cycle is completed. And, for late writing at the time of the next write request, the address and the data are taken into register circuits () upon the rising edge of the write enable signal (/WE).

Semiconductor storage device

A semiconductor memory device capable of accelerating address access and shortening cycle time is provided. A first address decoder () and first refresh address decoder () respectively decode an external address (Xn) supplied from outside the semiconductor memory device and a refresh address (RXn) used for refreshing within the semiconductor memory device. A multiplexer () selects the external address side decode signal (XnDm) or the refresh address side decode signal (XnRm) and outputs the signal as a decode signal (XnMm) based on an external address transmission signal (EXTR) and refresh address transmission signal (RFTR) so that a refresh operation and a read/write operation is performed continuously within one memory cycle. A word driver () then decodes decode signals (XnMm, XpMq) selected with multiplexer () and so forth, and activates a word line (WLmq).

A semiconductor memory device is provided which operates according to the specification of an SRAM, and which is capable of making the memory cycle shorter than heretofore, without normal access being delayed by the influence of refresh. An ATD circuit ( ) receives change of an address (&ldquo;Address&rdquo;), and generates a one shot pulse in an address transition detect signal (ATD) after an address skew period has elapsed. In the case of a write request, a write enable signal (/WE) is dropped within the address skew period. First, writing or reading is performed from the rising edge of the one shot pulse, and, in the case of writing, late writing is performed using the address and the data which were presented at the time of the directly preceding write request. Next, refresh is performed during the period from the falling edge of the one shot pulse until the address skew period of the subsequent memory cycle is completed. And, for late writing at the time of the next write request, the address and the data are taken into register circuits ( ) upon the rising edge of the write enable signal (/WE).

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Kanagawa, Japan

Hideo Inaba