Fujitsu Corporation

Fujitsu Semiconductor Limited

Hideo Akiyoshi

Hiroshi Shimizu

Hideyuki Amada

Tetsuo Ashizawa

2data transfer signal lines are provided between transmitting and receiving sides of data on n signal lines in order to reduce power consumption required for a data transfer even if the number of bits of data to be transferred increases. The transmitting side has an encoder for outputting a signal of a low potential to one signal line and a signal of a high potential to the other signal lines among the 2data transfer signal lines in response to an input of transfer data from the n signal lines. The receiving side has a decoder for outputting the similar data as the transfer data to n signal lines in response to inputs from the 2data transfer signal lines.

Data transfer system

A semiconductor memory includes: a plurality of regular memory cells; a first redundant memory cell; a second redundant memory cell; a first redundancy program circuit, first defect position information indicating a position of a first defective regular memory cell being programmed into the first redundancy program circuit; a second redundancy program circuit, second defect position information indicating a position of a second defective regular memory cell being programmed into the second redundancy program circuit; a redundancy switch circuit which couples signal lines to the regular memory cell, the first redundant memory cell, and the second redundant memory cell; and a redundancy signal switch circuit which replaces the first defect position information and the second defect position information with each other when the second defective regular memory cell is located between the first defective regular memory cell and the first redundant memory cell.

Semiconductor memory

A memory device includes a power supply line, a memory cell, a memory cell power supply node provided between the memory cell and the power supply line, a first voltage generating circuit coupled to the memory cell power supply node for supplying the memory cell power supply node with a first potential lower than a potential of the power supply line for a first period corresponding to at least a part of a writing operation period, and a second voltage generating circuit that is coupled to the memory cell power supply node for supplying the memory cell power supply node with a second potential lower than the potential of the power supply line for a second period corresponding to at least a part of the writing operation period.

Memory device

A driver circuit for a signal line of a large load is configured to include: a pMOS transistor having a source and a drain connected with a signal line and a ground line, respectively, and a gate receiving an input signal; and an nMOS transistor having a source and a drain connected with a signal line and a power supply line, respectively, and a gate receiving the input signal. As a result, the power consumption due to the signal line of a large load is reduced to realize a reduction of the power consumption of a semiconductor integrated circuit.

Semiconductor integrated circuit

At least one complete cell array having a predetermined memory capacity and an incomplete cell array having a capacity smaller than the predetermined memory capacity are arranged in one direction. The incomplete cell array is disposed closer to a signal control unit than the complete cell array. The signal control unit disposed on one-end side of a row of the cell arrays receives/outputs a signal from/to a global line. A read/write control unit disposed between the cell arrays controls data read/write from/to the cell arrays. The global line extends from one-end side of the row of the cell arrays to be connected to the read/write control unit. The global line is always wired on the short incomplete cell array, thereby reducing load capacitance and charge/discharge current thereof. This can reduce power consumption of a semiconductor memory, and shorten the access time thereof.

A cell array in the semiconductor memory device is divided into two blocks. Each of control signal lines for transmission of control signals are also divided into a first portion and a second portion correspondingly to the blocks. A repeater circuit that relays a control signal is provided between the two portions. The repeater circuit does not output the control signal from the first portion to the second portion, as long as a block that receives the control signal via the first portion is selected.

Semiconductor memory device

A latch circuit to perform high-speed input and output operations by reducing a load of an input circuit or an output circuit of the latch circuit. The latch circuit includes four or more inverters connected in a loop to hold a signal, a plurality of input terminals respectively connected to different nodes, and a plurality of output terminals respectively connected to different nodes. At least one input terminal of the latch circuit is used for normal operation of the latch circuit, and at least one input terminal is used for a test operation of the latch circuit. Further, at least one output terminal of the latch circuit is used for normal operation of the latch circuit, and at least one output terminal is used for a test operation of the latch circuit. The latch circuit reduces the number of circuit elements at a connecting point of an input terminal of the latch circuit or at a connecting point of an output terminal of the latch circuit. By reducing the number of circuit elements at the input or output connections, a load of the input or output can be reduced, and thereby high-speed input or output can be realized.

Latch circuit having reduced input/output load memory and semiconductor chip

A read circuit is connected to bit lines of different cell arrays in common, and determines a logical value of data read out onto any bit line of the cell arrays. An error correcting circuit corrects an error in the data read out onto a common read data line, and outputs the data as corrected data. In order to write back the corrected data into a memory cell from which the corrected data has been originally read out, write switches connect a common write data line through which the corrected data is transmitted, to a corresponding bit line. Thus, during a read cycle the corrected data can be written back to the memory cell.

Semiconductor memory including static memory

First dummy memory cells that store first logic and second dummy memory cells that store second logic that is reverse of the first logic are connected to a dummy word line. The first and second dummy memory cells are connected to a dummy bit line. A dummy sense amplifier activates a sense amplifier start signal for a real sense amplifier when the voltage of the dummy bit line varies. When real memory cells are read, the speed at which the first dummy memory cells cause the level of the dummy bit line to vary to the first logic level decreases due to the second logic level stored in the second dummy memory cells. The lower the threshold voltages of transistors, the more obvious this tendency becomes. Thus, the operation start timing of the sense amplifier can be optimally set even if a fabricating condition of a semiconductor memory varies.

The semiconductor integrated circuit is provided with a plurality of sub reset signal generators and a main reset signal generator. The sub reset signal generators respectively generate sub power-on reset signals whose timings differ from each other. The main reset signal generator generates a main power-on reset signal according to at least one from any of the sub power-on reset signals. Therefore, even where the characteristics of elements constituting the semiconductors integrated circuit change due to changes in the manufacturing conditions of the semiconductor integrated circuit, one of the sub power-on reset signals is generated at a normal timing. As a result, the main reset signal generator is able to generate a main power-on reset signal by using a normal sub power-on reset signal. That is, it is possible to constitute a power-on resetting circuit having a wide operation margin, wherein the internal circuits can be initialized without fault.

Power-on reset circuit/method for initializing an integrated circuit

A pulse generation circuit generates an output pulse that is set to its activated level in response to a leading edge of a set pulse. The pulse generation circuit comprises an output stage gate having a first output transistor for having the output pulse to be activated level and a second output transistor for having the output pulse to be deactivated level; a first inverter array, for propagating the set pulse and driving the first output transistor; a second inverter array, for propagating a reset pulse, and for driving the second output transistor. To prevent the trailing edge of the set pulse from being delayed, the pulse generation circuit comprises a reset transistor disposed at an inverter output in the first inverter array, being driven in response to the reset pulse propagating through the second inverter array.

Pulse generation circuit enabling its output pulse cycle to be shortened

The present invention is intended to realize reduction of time for supplying the pulse signal to the internal circuit. The setup time for latching (holding) the signal can be eliminated by generating a pulse signal without latching (holding) the input signal. A semiconductor integrated circuit is provided, which has a signal input circuit for receiving an input signal and outputting an address signal as a function of the input signal without holding the output signal. A pulse signal generating circuit is coupled to the signal input circuit for generating a pulse signal based on the output signal and a first clock signal.

Semiconductor integrated circuit and pulse signal generating method

Provided are first to fourth switch circuits of the same configuration as each other, each connected to complementary bus lines DB and *DB to be precharged to the same potential. In the-first switch circuit, switches and are connected between an input data signal line SI and the DB and between an input data signal line *SI and the *DB, respectively, and dummy switches and are connected between the SI and the *DB and between the *SI and the DB, respectively. Switches to are selectively on/off controlled by outputs of a decoder whereas dummy switches to are normally off.

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Kawasaki, Japan

Hideo Akiyoshi