Mitsubishi Electric Corporation

Fuji Electric Co., Ltd.

Hidenori Koketsu

Yusuke Miyata

Kenji Suzuki

Yuki Haraguchi

Yutaka Fukui

Rina Tanaka

Katsutoshi Sugawara

Hideyuki Hatta

Takuya Yoshida

Haruhiko Minamitake

Taiki Hoshi

Hiroshi Watanabe

Akihiro Koyama

Shiro Hino

Kazuhiro Mochizuki

Yasuyuki Kawada

Kohei Ebihara

Kensuke Taguchi

Kotaro Kawahara

Ryoji Kosugi

Akira Kiyoi

Shiyang Ji

Akemi Nagae

A first buffer layer includes: a first region containing protons and in contact with a drift layer; a second region between the first region and a first principal surface containing protons, and in contact with the first region; and a third region between the second region of the first buffer layer and the first principal surface. An impurity concentration profile of the first buffer layer includes: a maximum value in the second region; a kink at a boundary point between the first region and the second region, relaxing or stopping a decrease from the maximum value; a value at the boundary point higher than or equal to 80% of the maximum value; and a distribution of the third region longer than or equal to 5 μm and having an impurity concentration lower than the value at the boundary point and lower than or equal to 5.0×10/cm.

Semiconductor device

The present invention relates to a semiconductor device having trench gates. The semiconductor device includes the following: a first semiconductor layer; a first semiconductor region selectively disposed in the upper layer of the first semiconductor layer; a second semiconductor region in contact with the first semiconductor region; a third semiconductor region on the bottom surfaces of the first and second semiconductor regions; gate trenches provided to penetrate the first and third semiconductor regions in the thickness direction of the first and third semiconductor regions to reach the inside of the first semiconductor layer; a field-reducing region on the bottom of each gate trench; and connection layers arranged in the first semiconductor layer at intervals so as to be each in contact with at least one of sidewalls of the gate trenches, the connection layers each electrically connecting the field-reducing region to the third semiconductor region.

Semiconductor device and power converter

A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a diode trench gate, and an electrode layer. The first semiconductor layer is provided as a surface layer on the upper surface side of the semiconductor substrate. The second semiconductor layer is provided below the first semiconductor layer. The diode trench gate includes a diode trench insulation film formed along, out of the inner wall of the trench, a lower side wall and a bottom that are located below an upper side wall located on the upper end side of the trench. The diode trench gate includes a diode trench electrode provided inside the trench. The electrode layer covers the upper side wall of the trench. The first semiconductor layer is in contact with the electrode layer on the upper side wall of the trench.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device according to the present disclosure includes: a first conductivity-type silicon substrate including a cell part and a termination part surrounding the cell part in plan view; a first conductivity-type emitter layer provided on a front surface of the silicon substrate in the cell part; a second conductivity-type collector layer provided on a back surface of the silicon substrate in the cell part; a first conductivity-type drift layer provided between the emitter layer and the collector layer; a trench gate provided to reach the drift layer from a front surface of the emitter layer; and a second conductivity-type well layer provided on the front surface of the silicon substrate in the termination part. Vacancies included in a crystal defect in the cell part are less than vacancies included in a crystal defect in the termination part.

Semiconductor device and manufacturing method therefor

In a silicon carbide semiconductor device, an n-type drift layer is formed on a front surface of an n-type semiconductor substrate. Next, a trench is formed in the n-type drift layer, from a surface of the n-type drift layer. Next, a p-type pillar region is formed in the trench. A depth of the trench is at least three times a width of the trench. The p-type pillar region is formed by concurrently introducing a p-type first dopant and a gas containing an n-type second dopant incorporated at an atom position different from that of the first dopant.

Silicon carbide semiconductor device and a method of manufacturing a silicon carbide semiconductor device

An object of the present invention is to provide a silicon carbide semiconductor device with which the electric field at the time of switching is relaxed and the element withstand voltage can be enhanced. The distance between the outer peripheral end of a second surface electrode and the inner peripheral end of a field insulation film is smaller than the distance between an outer peripheral end of the second surface electrode and an inner peripheral end of the field insulation film in the case where the electric field strength applied to the outer peripheral lower end of the second surface electrode is calculated so as to become equal to the smallest dielectric breakdown strength among the dielectric breakdown strength of the field insulation film and the dielectric breakdown strength of the surface protective film at the time of switching when the value of dV/dt is greater than or equal to 10 kV/&#x3bc;s.

Silicon carbide semiconductor device

Growing community of inventors

Tokyo, Japan

Hidenori Koketsu