Nec Corporation

Nec Electronics Corporation

Hidemitsu Mori

Toru Tatsumi

Naoki Kasai

Hiromitsu Hada

Seiichi Takahashi

Koichi Takemura

Sota Shinohara

Yasuhiro Tsujita

Takeshi Nakura

In a semiconductor memory, a barrier layer formed of a first metal film, a metal nitride film and a second metal film laminated in the named order is formed under a lower electrode of a ferroelectric capacitor in a memory cell, in order to minimize a pealing and lifting of the lower electrode from an underlying plug in the process of forming a ferroelectric material film as a capacitor dielectric film and in its succeeding annealing process. The metal nitride film is formed of a nitride of a metal constituting the first or second metal film.

Semiconductor memory and process for fabricating the same

An interlayer insulating film, contacts, and wirings are formed on a MOS transistor formed on a silicon substrate. Another interlayer insulating film and contacts are formed thereon. Subsequently, as a first heat treatment, a heat treatment is performed in a hydrogen atmosphere or a nitrogen- or otherwise-diluted hydrogen atmosphere at a temperature of the order of 300-500&deg; C. for about 5-60 minutes, thereby recovering defects that occur in the MOS transistor and insulating film forming steps and the like. Then, a ferroelectric capacitor connected to either diffusion layer of the MOS transistor is formed along with wirings, electrodes, and the like. Thereafter, as a second heat treatment, a heat treatment is performed in nitrogen at a temperature of the order of 300-500&deg; C. for about 5-60 minutes. This recovers defects that occur after the first heat treatment step.

Method of fabricating semiconductor device having ferroelectric capacitor

A ferroelectric memory is composed of a wiring layer, a bottom electrode coupled to the wiring layer, a ferroelectric film formed on the bottom electrode, a top electrode formed on the ferroelectric film, and a metal silicide layer coupled to the top electrode and located above the ferroelectric film. The wiring layer includes substantially no silicon.

Ferroelectric memory including ferroelectric capacitor, one of whose electrodes is connected to metal silicide film

The invention relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate, a first etching stopper insulating film, a first insulating interlayer, a pair of first contact holes, first buried conductive layers, a first interconnection formed on one of the first buried conductive layers, a second insulating interlayer, a second contact hole, a second buried conductive layer, and a second interconnection. The first contact holes are formed at a predetermined interval in a direction parallel to the surface of the semiconductor substrate so as to reach a semiconductor element formed on the semiconductor substrate through the first insulating interlayer and the etching stopper insulating film. The second contact hole is formed to reach the other first buried conductive layer through the second insulating interlayer corresponding to a portion above the first buried conductive layer. Each of the first contact holes is constituted by a small-diameter lower contact hole formed in the first etching stopper insulating film and a large-diameter upper contact hole formed in the first insulating interlayer, and the first buried conductive layers do not project from the surface of the first insulating interlayer.

Method of making a semiconductor device with an etching stopper

A method of fabricating a semiconductor device using the steps of: (a) forming a large number of first transistors having a fixed gate electrode separation in a first region on a semiconductor substrate and forming a large number of second transistors having a gate electrode separation wider than that of the first transistors in a second region on the semiconductor substrate; (b) covering the entire surface of these first and second regions with an insulating film of fixed film thickness; and (c) forming a buried layer consisting of the insulating film between the gate electrodes of the first transistors by etching this entire insulating film and forming side walls consisting of the insulating film on electrodes of the second transistors. In step (c), the spaces between the gate electrodes of the first transistors are filled with insulating film in self-aligned fashion and side walls consisting of insulating film are formed on the gate electrodes of the second transistors so that the space between the gate electrodes, i.e. the diffusion layer of the first transistors, is covered with insulating film and is not exposed to the etching atmosphere.

Method of making transistors in an IC including memory cells

On a main surface of a silicon substrate of one conductivity type, a diffusion layer of the opposite conductivity type is formed, and the main surface of the silicon substrate is covered by an insulator film. The insulator film is formed with a contact hole which extends to reach the diffusion layer of the opposite conductivity type. A contact plug is provided in the contact hole. The contact plug fills the contact hole and comprises a first silicon layer of the opposite conductivity type directly connected to the diffusion layer of the opposite conductivity type, a silicon-germanium alloy layer of the opposite conductivity type directly contact to the first silicon layer, and a second silicon layer of the opposite conductivity type directly contact to the silicon-germanium alloy layer. Wiring is provided on the surface of the insulator film in direct contact to the contact plug. As a result, increase in leakage at the junction of the diffusion layer is prevented by the low-resistance contact plug including the silicon-germanium alloy.

Method for manufacturing a semiconductor device having contact plug made

A memory cell of a semiconductor dynamic random access memory device requires a bit line contact hole open to a drain region of a cell transistor for connecting a bit line to the drain region and a node contact hole open to a source region for connecting a storage electrode of a stacked capacitor to the source region, and the bit line contact hole and the node contact hole are plugged with silicon layers; the silicon layers are epitaxially grown from the source and drain regions over an oxide-encapsulated gate electrode of the cell transistor so as to increase the contact areas; and the silicon layers are firstly anisotropically grown until reaching the upper surface of the oxide-encapsulated gate electrode, and, thereafter, isotropically grown so as to increase the contact areas.

Process for fabricating semiconductor device having semiconductor layers

Semiconductor device having contact plug and method for manufacturing

A silicon layer serving as a contact plug directly connected to a diffusion layer of a MOS transistor is provided. On a surface of an N.sup.- type diffusion layer in self-alignment with a silicon nitride layer spacer and a field oxide layer, an N.sup.+ type monocrystalline silicon layer formed by anisotropic selective epitaxial growth method is directly connected. The surface of the N.sup.+ type monocrystalline silicon layer is directly connected to an N.sup.+ type monocrystalline silicon layer formed by isotropic selective epitaxial growth.

Semiconductor device and fabrication process thereof

In semiconductor memory device, word lines (2a) are arranged in parallel to each other on a semiconductor substrate (9). Each of the device active regions (1) has first oblique intersection portions (1a) which obliquely intersect adjacent two of the word lines (2a) in first oblique directions with a distance left between each of the device active regions (1) and the adjacent two of the word lines (2a). Each of bit lines (4) has second oblique intersection portions (4a) which obliquely intersect the adjacent two of the word lines (4) in second oblique directions reverse with respect to the first oblique directions with another distance left between each of the bit lines (4) and the adjacent two of the word lines (2a). The first oblique directions of the first oblique intersection portions (1a) of each of the device active regions (1) are reversed at every memory cell (or at every two memory cells). The second oblique directions of the second oblique intersection portions (4a) of each of the bit lines (4) are reversed at every memory cell (or at every two memory cells).

Semiconductor memory device capable of realizing a minimum memory cell

The invention relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate, a first etching stopper insulating film, a first insulating interlayer, a pair of first contact holes, first buried conductive layers, a first interconnection formed on one of the first buried conductive layers, a second insulating interlayer, a second contact hole, a second buried conductive layer, and a second interconnection. The first contact holes are formed at a predetermined interval in a direction parallel to the surface of the semiconductor substrate so as to reach a semiconductor element formed on the semiconductor substrate through the first insulating interlayer and the etching stopper insulating film. The second contact hole is formed to reach the other first buried conductive layer through the second insulating interlayer corresponding to a portion above the first buried conductive layer. Each of the first contact holes is constituted by a small-diameter lower contact hole formed in the first etching stopper insulating film and a large-diameter upper cyontact hole formed in the first insulating interlayer, and the first buried conductive layers do not project from the surface of the first insulating interlayer.

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Tokyo, Japan

Hidemitsu Mori