Kabushiki Kaisha Toshiba

Hidemi Ishiuchi

Tsutomu Sato

Ichiro Mizushima

Satoshi Matsuda

Kazumi Inoh

Koji Sakui

Nobuo Hayasaka

Chiaki Takubo

Mie Matsuo

Toshiharu Watanabe

Tsunetoshi Arikado

Kinuyo Tanaka

A semiconductor device includes a semiconductor substrate, cavities, and an element isolating region. The cavities, which are each shaped like a flat plate, are made in the semiconductor substrate. The element isolating region is formed in the surface of the semiconductor substrate and located at the sides of the cavities.

Semiconductor device with a cavity therein and a method of manufacturing the same

Provided is a stacked type semiconductor device formed of a plurality of semiconductor integrated circuit devices stacked, each having a specification and including a semiconductor integrated circuit chip, wherein at least three of the semiconductor integrated circuit devices are stacked in the order of a value of the specification.

Stacked type semiconductor device

A trench dual-gate MOSFET comprises a projection which is bent to enclose a predetermined region on a semiconductor substrate of a first conductivity type. This projection is defined by a trench formed by selectively removing the surface region of the semiconductor substrate. A gate insulation film is formed on the side wall of the projection and on the semiconductor substrate portion located around the base of the projection. A gate electrode is formed on the side wall of the projection and on the semiconductor substrate portion located around the base of the projection, with the gate insulation film interposed and in a manner to surround the projection. A first impurity region of a second conductivity type, which serves as either a source or drain region, is formed in the top portion of the projection. A second impurity region of the second conductivity, which serves as either a drain or source region, is formed in the surface region of that portion of the semiconductor substrate which is located around the base of the projection.

Trench dual-gate MOSFET

A method of manufacturing a MOS semiconductor device which comprises a first step of forming a p-type well region in the surface of an n-type silicon substrate, a second step of forming a field oxide layer surrounding part of the surface of the well region, a third step of ion-implanting a n-type impurity into the surface of the well region, to reduce the carrier density of the well region in the vicinity of the ion-implanted without changing the conductivity type of the well region, a fourth step of forming a gate electrode insulatively on the ion-implanted surface of the well region, and a fifth step of forming the n.sup.+ -type source and drain regions in the ion-implanted surface of the well region. The third step of this manufacturing method uses the field oxide layer for implanting the n-type impurity, as a mask.

Method of manufacturing a memory cell for a dynamic type random access

Growing community of inventors

Yokohama, Japan

Hidemi Ishiuchi