Renesas Technology Corp.

Hitachi, Ltd.

Renesas Electronics Corporation

Other

Hideki Yasuoka

Masami Koketsu

Keiichi Yoshizumi

Kunihiko Kato

Kazunari Saitou

Masami Kouketsu

Susumu Ishida

Kazuhisa Higuchi

Masatoshi Taya

Takayuki Nakaji

Yoshiaki Kamigaki

Shinichi Minami

Yasuhiro Takeda

Shigeya Toyokawa

Fukuo Owada

Norio Anzai

Akira Muramatsu

Yasunobu Tanizaki

The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.

Semiconductor device comprising a Schottky barrier diode

A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.

Semiconductor device and a method of manufacturing the same

Semiconductor device comprising a schottky barrier diode

Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.

Method of manufacturing semiconductor integrated circuit device with high and low breakdown-voltage MISFETs

With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, ntype semiconductor regions, each having a conduction type opposite to ptype semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions spaced away from ptype semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the ptype semiconductor regions (on the drain side, in particular). The ntype semiconductor regions extend to positions deeper than the trench type isolation portions.

Semiconductor device with MISFET that includes embedded insulating film arranged between source/drain regions and channel

Semiconductor integrated circuit device with high and low breakdown-voltage MISFETs

A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.

Method of manufacturing a semiconductor device that includes a process for forming a high breakdown voltage field effect transistor

A manufacturing technique for a zener diode which includes forming a first semiconductor region in a region such as a well region at a primary face of a semiconductor substrate and then forming a second semiconductor region of opposite conductivity type thereover. The second semiconductor region covers an area greater than the underlying first semiconductor region. The method further calls for forming an insulating film on the primary face of the substrate followed by the forming connection holes in the insulating film to expose an upper part of the second semiconductor region located outside the area covered by the junction affected between the first and second semiconductor regions. This is followed by the formation of a wire at the upper part of the insulating film in which an electrical connection is affected between the wire and the second semiconductor region through the plural connection holes which are distributively arranged.

Method of manufacturing a semiconductor integrated circuit device

A plurality of connection holes for connecting n type semiconductor region of zener diodes (D , D ) and wires and to each other are not arranged in the center of the n type semiconductor region , that is, in a region in which a p type semiconductor region and the n type semiconductor region form a junction but is arranged in the periphery which is deeper than the center in junction depth. In addition, these connection holes are spaced from each other so that a pitch between the adjacent connection holes is greater than a minimum pitch between connection holes of the circuit, and thereby a substrate shaving quantity is reduced when the respective connection holes are formed by means of dry etching.

Semiconductor integrated circuit device and method of manufacturing the same

Growing community of inventors

Tokyo, Japan

Hideki Yasuoka