Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Hideki Genjo

Yoshinori Okumura

Atsushi Hachisuka

Ikuo Ogoh

Atsuhiro Fujii

Hideaki Arima

Masazumi Matsuura

Shigeru Shiratake

Koji Taniguchi

Hideo Kotani

Yuichi Nakashima

Shigeo Nagao

Kohjiroh Yuzuriha

Masao Nagatomo

Eiji Hasunuma

Takayuki Matsukawa

Yasuhiro Ido

Toshihiko Minami

In the semiconductor device, in order to meet the demand of reduced diameter of a contact hole along with the miniaturization of the semiconductor device, an anti-HF side wall film which is not etched by a hydrofluoric acid, formed of an isolating film such as nitride film, is provided on the side wall of contact hole. Further, a second impurity region which is connected to one of the pair of n type source/drain regions and a first impurity region reaching a p type isolation region are provided in silicon substrate near the lower end of contact hole. Because of this structure, it becomes possible to prevent expansion of the diameter for forming the interconnection layer, as desired in the miniaturized semiconductor device, and therefore a semiconductor device and manufacturing method thereof which stabilize operation characteristic of the semiconductor device can be provided.

Semiconductor device having interconnection structure

A semiconductor device has a plurality of fuse members (1a, 1b) composed of a metal that can be cut by laser light (4), disposed over a semiconductor substrate (5). The length L of the fuse members (1a, 1b) is smaller than a value obtained by subtracting an alignment error .alpha. of the laser light (4) from a spot diameter D of the laser light (4), i.e., the value (D-.alpha.). The fuse members (1a, 1b) are spaced a distance l larger than a value obtained by adding the alignment error .alpha. to the half of the spot diameter D, i.e., the value (D/2+.alpha.).

Semiconductor device having a metallic fuse member and cutting method

The method of forming an interlayer insulating film insulating first and second layers of conductor patterns in a semiconductor device includes the steps of preparing a reaction gas including at least ozone and silicon alkoxide, wherein the ratio of ozone with respect to silicon alkoxide is adjusted to be not less than 5 within the reaction gas, and forming an insulating film by CVD reacting the reaction gas at atmospheric pressure at the temperature of 350.degree. C.- 450.degree. C., whereupon the interlayer insulating film includes at least the insulating film formed by atmospheric pressure CVD reaction.

Method of manufacturing semiconductor device including interlaying

A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layer disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

Manufacturing method of an electrically programmable non-volatile memory

A memory cell of a semiconductor memory device comprises one MOS transistor (3) and one stacked capacitor (4). One of the source/drain regions (8a, 8b) of the MOS transistor is connected to a bit line (2a, 2b). The bit line is formed from a contact portion to the source/drain regions of the MOS transistor to a portion above the stacked capacitor. The bit line is formed of a metal having high melting point, a silicide of a metal having high melting point or a polycide. Since this material has low reflectance against exposing light, the precision in patterning the interconnection is improved.

Semiconductor memory device having bit lines formed of an

The method of forming an interlayer insulating film insulating first and second layers of conductor patterns in a semiconductor device includes the steps of preparing a reaction gas including at least ozone and silicon alkoxide, wherein the ratio of ozone with respect to silicon alkoxide is adjusted to be not less than 5 within the reaction gas, and forming an insulating film by CVD reacting the reaction gas at atmospheric pressure at the temperature of 350.degree. C.-450.degree. C., whereupon the interlayer insulating film includes at least the insulating film formed by atmospheric pressure CVD reaction.

Semiconductor device including interlayer insulating film

A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layers disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.

Electrically programmable non-volatile memory device and manufacturing

A method of manufacturing a semiconductor device in which an element is flattened by improving a technique of forming an interlayer insulating film. A thick insulating film having a film thickness necessary for a convexo-concave pattern to be flattened is deposited on a semiconductor substrate comprising the convexo-concave pattern of an element, a wiring and the like. Then, the thick insulating film is etched until it becomes a predetermined film thickness to form an interlayer insulating film having a predetermined film thickness from said thick insulating film. At this time, since acid and water are attached on the surface of the interlayer insulating film, a new film is formed on the surface of the interlayer insulating film to cover this water and acid. Then, a resist pattern having a desired configuration is formed on this new film. A contact hole is formed on the interlayer insulating film using this resist pattern. Thereafter, a wiring pattern electrically connected to the element is formed on the interlayer insulating film through the contact hole. According to this method, since the acid and water attached on the interlayer insulating film are covered with the new film, the adhesion between the interlayer insulating film and the resist is improved. As a result, the contact hole can be opened reliably, whereby the element is surely connected to the wiring pattern and a semiconductor device can be provided with high reliability.

Growing community of inventors

Hyogo, Japan

Hideki Genjo