Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Renesas Technology Corp.

Hidekazu Oda

Hirokazu Sayama

Kazunobu Ohta

Kouhei Sugihara

Kazunobu Ota

Toshiaki Iwamatsu

Shuichi Ueno

Tomohiro Yamashita

Satoshi Shimizu

Takehisa Yamaguchi

Takashi Kuroi

Yoshiki Yamamoto

Hirofumi Shinohara

Masaaki Shinohara

Takaaki Tsunomura

Yukio Nishida

Toshiyuki Oishi

Kiyoteru Kobayashi

Yasuo Inoue

Shigeru Kusunoki

Shinichi Satoh

Masahiro Yoneda

Koichi Moriizumi

Yoshio Kohno

Masahiro Hatanaka

Tadashi Nishimura

Katsuyuki Horita

Shuji Nakao

Shigeki Komori

Katsuomi Shiozawa

Yasuyoshi Itoh

Masashi Kitazawa

Hiroshi Morita

Kohei Sugihara

Shuuichi Ueno

Hiromasa Yoshimori

Takahashi Hayashi

A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same

On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

Method of manufacturing semiconductor device

Semiconductor device and manufacturing method of the same

To suppress performance degradation of a semiconductor device, when the width of a first active region having a first field effect transistor formed therein is smaller than the width of a second active region having a second field effect transistor formed therein, the height of a surface of a first raised source layer of the first field effect transistor is made larger than the height of a surface of a second raised source layer of the second field effect transistor. Moreover, the height of a first surface of a raised drain layer of the first field effect transistor is made larger than a surface of a second raised drain layer of the second field effect transistor.

Semiconductor device and method of manufacturing the same

To enhance reliability and performance of a semiconductor device that has a fully-depleted SOI transistor, while a width of an offset spacer formed on side walls of a gate electrode is configured to be larger than or equal to a thickness of a semiconductor layer and smaller than or equal to a thickness of a sum total of a thickness of the semiconductor layer and a thickness of an insulation film, an impurity is ion-implanted into the semiconductor layer that is not covered by the gate electrode and the offset spacer. Thus, an extension layer formed by ion implantation of an impurity is kept from entering into a channel from a position lower than the end part of the gate electrode.

A semiconductor device includes an SOI substrate and a MISFET formed on the SOI substrate. The SOI substrate has a base substrate, a ground plane region formed on the base substrate, a BOX layer formed on the ground plane region and an SOI layer formed on the BOX layer. The base substrate is made of silicon and the ground plane region includes a semiconductor region made of silicon carbide.

Semiconductor device having a field effect transistor formed on a silicon-on-insulator substrate and manufacturing method thereof

A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000&#xb0; C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.

A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate () in a low-voltage NMOS region (LNR) thereby to form extension layers (). Then, a silicon oxide film (OX) is formed to cover the whole surface of the silicon substrate (). The silicon oxide film (OX) on the side surfaces of gate electrodes (-) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate () in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers () later to be extension layers ().

Method of manufacturing semiconductor device with offset sidewall structure

Growing community of inventors

Tokyo, Japan

Hidekazu Oda