Panasonic Intellectual Property Management Co., Ltd.

Matsushita Electronics Corporation

Hidekazu Nakamura

Manabu Yanagihara

Takeshi Kawabata

Katsumi Otani

Tomohiko Nakamura

Yusuke Katagiri

Hideaki Nakura

Jutarou Kotani

Isamu Kawashima

A semiconductor device that is a surface mount-type device includes a nitride semiconductor chip including a silicon substrate having a first thermal expansion coefficient and an InGaAlN layer in contact with a surface of the silicon substrate, where 0≤x≤1, 0≤y≤1, 0≤x+y≤1; and a die pad including Cu and having a second thermal expansion coefficient that is greater than the first thermal expansion coefficient. A thickness of the nitride semiconductor chip is at least 0.2 mm, length L of the nitride semiconductor chip is at least 3.12 mm, and thickness tm of the die pad and length L of the nitride semiconductor chip satisfy tm≥2.00×10×L+0.173, tm being a thickness in mm and L being a length in mm.

Semiconductor device and method for manufacturing the same

A semiconductor device that is a surface mount-type device includes a nitride semiconductor chip including a silicon substrate having a first thermal expansion coefficient and an InGaAlN layer in contact with a surface of the silicon substrate, where 0&#x2264;x&#x2264;1, 0&#x2264;y&#x2264;1, 0&#x2264;x+y&#x2264;1; and a die pad including Cu and having a second thermal expansion coefficient that is greater than the first thermal expansion coefficient. A thickness of the nitride semiconductor chip is at least 0.2 mm, length L of the nitride semiconductor chip is at least 3.12 mm, and thickness tm of the die pad and length L of the nitride semiconductor chip satisfy tm&#x2265;2.00&#xd7;10&#xd7;L+0.173, tm being a thickness in mm and L being a length in mm.

A semiconductor device provided with a wide and shallow first groove and a second groove in the first groove area, having a narrower width than that of the first groove around a predetermined area in a one-conductive area provided in the upper region of a semiconductor substrate as a mesa groove, wherein at least the second groove is covered with an electrical insulator. The upper surface of the electrical insulator is located approximately as high as or lower than the upper surface of the electrical insulating film. Thus, especially in a mesa semiconductor device with a high-voltage resistance, an insulating protective layer having a sufficient thickness can be formed stably over the entire region of a mesa groove. As a result, the variation in high-voltage resistance characteristics can be decreased and the processing yield affected by breakage or cracking in the mesa groove region during subsequent processes caused by the formation of the mesa groove can be improved greatly.

Growing community of inventors

Osaka, Japan

Hidekazu Nakamura