Hitachi, Ltd.

Renesas Electronics Corporation

Hitachi Power Semiconductor Device, Ltd.

Hidekatsu Onose

Michio Ohue

Yutaka Kobayashi

Ryuichi Saito

Natsuki Yokoyama

Atsuo Watanabe

Tsutomu Yatsuo

Kazuhiro Mochizuki

Toshiyuki Ohno

Shuroku Sakurada

Norifumi Kameshiro

Yuji Takayanagi

Katsumi Ishikawa

Shin Kimura

Kozo Sakamoto

Haruka Shimizu

Takayuki Iwasaki

Susumu Murakami

Saburo Oikawa

Hiroyuki Takazawa

Yasuhiro Mochizuki

Sunao Funakoshi

Hideo Kobayashi

Masayoshi Naito

Satoshi Matsuyoshi

Hideo Homma

Yukimasa Satou

Saburou Oikawa

A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4&#xd7;10cmor higher and 6&#xd7;10cmor lower and an impurity concentration in a second JTE region is set to 2&#xd7;10cmor lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6&#xd7;10cmor higher and 8&#xd7;10cmor lower and an impurity concentration in the second JTE region is set to 2&#xd7;10cmor lower in a case of a junction barrier Schottky diode.

Semiconductor device with substantially equal impurity concentration JTE regions in a vicinity of a junction depth

Semiconductor device with similar impurity concentration JTE regions

For suggesting a structure capable of achieving both a low start-up voltage and high breakdown voltage, a SiC vertical diode includes a cathode electrode, an ncathode layer, an ndrift layer on the ncathode layer, a pair of pregions, an nchannel region formed between the ndrift layer and the pregion and sandwiched between the pair of pregions, nanode regions and an anode electrode formed on the nanode regions and the pregions.

Semiconductor device

A driver circuit that lowers the dependence of the loss in the wide gap semiconductor device upon the temperature is provided. A gate driver circuit for voltage driven power semiconductor switching device includes a power semiconductor switching device, a driver circuit for supplying a drive signal to a gate terminal of the switching device with reference to an emitter control terminal or a source control terminal of the switching device, and a unit for detecting a temperature of the switching device. The temperature of the power semiconductor switching device is detected, and a gate drive voltage or a gate drive resistance value is changed based on the detected temperature.

Driver circuit for switching device

A semiconductor device having a junction FET having improved characteristics is provided. The semiconductor device has a junction FET as a main transistor and has a MISFET as a transistor for control. The junction FET has a first gate electrode, a first source electrode, and a first drain electrode. The MISFET has a second gate electrode, a second source electrode, and a second drain electrode. The MISFET is an n-channel type MISFET and has electric characteristics of an enhancement mode MISFET. The second gate electrode and the second drain electrode of the MISFET are connected to each other by short-circuiting. The first gate electrode of the junction FET and the second source electrode of the MISFET are connected to each other by short-circuiting.

Semiconductor device having a junction FET and a MISFET for control

A junction FET having a large gate noise margin is provided. The junction FET comprises an nlayer forming a drift region of the junction FET formed over a main surface of an nsubstrate made of silicon carbide, a player forming a gate region formed in contact with the nlayer forming the drift region and a gate electrode provided in an upper layer of the nsubstrate. The junction FET further incorporates pn diodes formed over the main surface of the nsubstrate and electrically connecting the player forming the gate region and the gate electrode.

Semiconductor device with large blocking voltage

In a bipolar device, such as transistor or a thyristor, the emitter layer or the anode layer is formed of two high-doped and low-doped layers, a semiconductor region for suppressing recombination comprising an identical semiconductor having an impurity density identical with that of the low-doped layer is present being in contact with a base layer or a gate layer and a surface passivation layer, and the width of the semiconductor region for suppressing recombination is defined equal with or longer than the diffusion length of the carrier. This provides, among other things, an effect of attaining reduction in the size of the bipolar transistor or improvement of the switching frequency of the thyristor without deteriorating the performance.

Bipolar device and fabrication method thereof

A UMOSFET is capable of reducing a threshold voltage and producing a large saturation current. A typical UMOSFET according to the present invention includes: an Ntype SiC substrate constituting a drain layer; an Ntype SiC layer that is in contact with the drain layer and constitutes a drift layer; a P type body layer formed on the drift layer and being a semiconductor layer; an Ntype SiC layer constituting a source layer; a trench extending from the source layer to a predetermined location placed in the drift layer; a P type electric field relaxation region provided around and outside a bottom portion of the trench; and a channel region extending from the Ntype source layer to the P type electric field relaxation region and having an impurity concentration higher than that of the Ntype drift layer and lower than that of the P type body layer.

Semiconductor device and electrical circuit device using thereof

A structure is provided that ensures a low on-resistance and a better blocking effect. In a lateral type SIT (Static Induction Transistor) in which a first region is used as a pgate and a gate electrode is formed on the bottom of the first region, the structure is built such that the pgate and an nsource are contiguous. An insulating film is formed on the surface of an nchannel, and an auxiliary gate electrode is formed on the insulating film. In addition, the auxiliary gate electrode and the source electrode are shorted.

A semiconductor memory device has a plurality of memory cells in an array, into which the memory cells data is writable, and which can subsequently be read. Each memory cell has a switching element with one terminal connected to a bit line of the array another terminal connected to at least one ferroelectric capacitor, and a control terminal connected to a word line. The cell may then be operated to detect the change in polarization of the ferroelectric capacitor when a voltage is applied which is not sufficient to cause a change of state of the ferroelectric capacitor. Alternatively, a ferroelectric capacitor and a capacitor other than a ferroelectric capacitor is connected to the switching element. In a further alternative, a plurality of ferroelectric capacitors are connected to the switching element, so that different data are writable into each.

Semiconductor memory device and methods of operation thereof

A semiconductor device includes a trench formed on a source side of a drift region, a p-type gate region and a gate formed at the bottom of the trench, and the source formed over the entire surface of the unit device through an insulating film. The narrowest portion of a channel of the device is deeper than one-half the junction depth of the p-type gate region. This allows the width of the channel on the drain side to be reduced even when a lower energy ion implantation manufacturing process is used.

In a static induction transistor, in addition to a first gate layer ( ), a plurality of second gate layers ( ) having a shallower depth and a narrower gap therebetween than those of the first gate layer ( ) are provided in an area surrounded by the first gate layer ( ), thereby an SiC static induction transistor with an excellent off characteristic is realized, while ensuring a required processing accuracy during production thereof.

Static induction transistor

To reduce the field intensity on the termination surface, almost not affecting the on-characteristic, a drift layer is made of two layers, an n-layer and n layer, and a termination region is formed on the surface of the above n layer. An impurity concentration ratio between the n layer and the n-layer is less than 1:2, and the thickness of the n layer is less than that of a source n layer. Reliability can be secured even in a high temperature operation.

Semiconductor device and power converter using the same

A wide bandgap semiconductor single crystal is applied as a semiconductor substrate material of a semiconductor surge absorber, and a surge absorption operation starting voltage is set by a punchthrough of a pn junction, to obtain a semiconductor surge absorber with a repetitive operation and a high surge endurance.

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Hitachi, Japan

Hidekatsu Onose