Ricoh Company, Ltd.

Hideji Miyanishi

Kazumasa Aoki

Kenji Motohashi

Kikuo Kazama

Toshinobu Shoji

Takashi Yanagimoto

A printed wiring board includes a bridge located in a surface layer, a noise absorber located on the bridge, a plurality of grounds directly connected or high-frequency-connected to the bridge, a first device using one of the plurality of grounds as a reference potential, a second device using one of the plurality of grounds other than the ground for the first device as a reference potential, and a high-speed signal line that connects the first device and the second device. The high-speed signal line is routed through a layer adjacent to the bridge in a layer direction of the printed wiring board to form a transmission line structure.

Printed wiring board

A printed wiring board, which may be included in an electronic apparatus, includes a pair of signal pads including a first signal pad and a second signal pad formed on a front side thereof and configured to transmit differential signals, a ground pad formed at a position in proximity to the pair of signal pads, and a via configured to connect the ground pad to a ground pattern formed either on a back side or on an inner layer of the printed wiring board directly or via a lead wire led out from the ground pad. The via is located at a substantially equal position spaced away from the first signal pad and the second signal pad.

Printed wiring board and electronic apparatus including same

An electromagnetic field analysis apparatus includes an information input device configured to input information as to wirings and components of an analysis object and a modeling device configured to generate a simulation model of the analysis object based on the inputted information as to wirings and components of the analysis object. A model simplification device simplifies the simulation model into a simplified simulation model by dividing the analysis object according to the simulation model into a plurality of cells and thinning out, when a plurality of elements are included in a cell, the plurality of elements.

Electromagnetic field analysis apparatus, method and computer program

A noise injection apparatus for injecting noise to a printed circuit board is disclosed that includes a signal generator that generates noise, a coaxial cable having one end connected to an output of the signal generator, and a probe that is connected to another end of the coaxial cable and is configured to convey the noise generated by the signal generator to a power supply and a ground pin of a device element of the printed circuit board via the coaxial cable.

Noise injection apparatus for printed circuit board

A testing method for measuring electromagnetic interference of a noise on a to-be-tested printed circuit board, has the steps of: a) injecting a signal simulating an expected noise of a predetermined device mounted on the to-be-tested printed circuit board, into the to-be-tested printed circuit board, in a condition in which at least the predetermined device is not actually mounted on the to-be-tested printed circuit board; and b) measuring electromagnetic interference of the signal.

Testing method/arrangement measuring electromagnetic interference of noise in a to-be-tested printed circuit board

A design rule for a printed wiring board is provided. A conductive layer and a pad are separate from each other in a distance defined by the design rule, which sufficiently prevents the capacitance coupling between the conductive layer and the pad.

Printed wiring board with a plurality of pads and a plurality of conductive layers offset from the pads

There is provided a potential comparing circuit of which output potential is almost equal to specific determining potential levels used in a next-stage logic circuit. The potential comparing circuit has a current-mirror circuit, a first transistor, a second transistor and an offset correcting circuit. The current-mirror circuit is connected to a first power source. The first transistor has a gate to which a first input signal is supplied. The second transistor has a gate to which a second input signal is supplied, a channel type of the second transistor being the same as a channel type of the first transistor. The offset correcting circuit is provided between a drain of the first transistor and an input point of the current-mirror circuit, for correcting a potential level obtained at a drain of the first transistor to correspond to specific potential levels related to the specific determination potential levels. The output signal being output from a point between the drain of the second transistor and the output point of the current-mirror circuit.

Potential comparing circuit having an offset correcting circuit

A detecting amplifier has a first transistor arranged between a first positive power source and a semiconductor memory and connected in series to the first positive power source and having a low turning-on resistance value; a second transistor arranged between the first transistor and the semiconductor memory and connected in series to the first transistor and connected to a negative feedback circuit having an inverting element; and a third transistor arranged between a second positive power source and an output section of the detecting amplifier and connected in series to the second positive power source and constituting a current mirror structure together with the first transistor. In accordance with this detecting amplifier, an access time to a memory transistor is maintained in a short state and a detecting operation of the detecting amplifier is reliably performed.

Detecting amplifier with current mirror structure

A semiconductor memory device includes a pair of bit lines and a sense amplifier device. Each of the pair of bit lines has a parasitic capacitor and a memory cell connected thereto respectively. The memory cell has an electric capacity and a word line connected to a gate of a transistor. The sense amplifier device has a first sense amplifier, a second sense amplifier, a first transistor, a second transisitor and a third transistor for amplifying a potential difference caused by a balance between the parasitic capacitor of one bit line and the electric capacity of one memory cell connected to the one bit line after the pair of bit lines are precharged and the word line of the one memory cell is raised.

Growing community of inventors

Kanagawa, Japan

Hideji Miyanishi