Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Nanjing Company, Limited

TSMC China Company Limited

Hidehiro Fujiwara

Yen-Huei Chen

Hung-Jen Liao

Chih-Yu Lin

Hsien-Yu Pan

Wei-Chang Zhao

Jonathan Tsung-Yung Chang

Yi-Hsin Nien

Haruki Mori

Yih Wang

Sahil Preet Singh

Li-Wen Wang

Mahmut Sinangil

Ching-Wei Wu

Kao-Cheng Lin

Chia-En Huang

Yasutoshi Okuno

Wei-Min Chan

Chiting Cheng

Yangsyu Lin

Yu-Hao Hsu

Chien-Chen Lin

Lee-Chung Lu

Hong-Chen Cheng

Jui-Che Tsai

Tetsu Ohtou

Chien-Chi Tien

Zhi-Hao Chang

Yen-huei Chen

Feng-Lun Chen

Wei-Cheng Wu

Yu-Der Chih

Yun-Han Lee

Yi-Chun Shih

Chia-Fu Lee

Hiroki Noguchi

Yi-Hsun Chiu

Wei Min Chan

Tze-Chiang Huang

He-Zhou Wan

Po-Hao Lee

Yusuke Oniki

Xiu-Li Yang

Chun-Hao Chang

Ming-En Bu

Ru-Yu Wang

Tzu-hsien Yang

Shih-Lien Linus Lu

Ming-Yi Lee

Cheng Chun Dai

Mohammed Hasan Taufique

Zhi-hao Chang

A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells; each of the bit cells being coupled correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including local write drivers correspondingly coupled to the segments; and a global write driver coupled to each of the local write drivers.

Semiconductor device including distributed write driving arrangement

A memory circuit includes a first pull down transistor, a first pass gate transistor coupled to the first pull down transistor, a second pull down transistor, a second pass gate transistor and a first metal contact. The second pull down transistor has a first active region located on a first level. The second pass gate transistor has a second active region located on the first level, and being coupled to the second pull down transistor. The first metal contact extends from the first active region to the second active region, being located on a second level, and electrically coupling a drain of the second pull down transistor to a drain of the second pass gate transistor. The first pass gate transistor, the second pass gate transistor, the first pull down transistor and the second pull down transistor are part of a four transistor (4T) memory cell.

Memory array circuit and method of manufacturing same

Disclosed herein are related to a memory device. In one aspect, a memory device includes a set of memory cells. In one aspect, the memory device includes a first bit line extending along a direction. The first bit line may be coupled to a subset of the set of memory cells disposed along the direction. In one aspect, the memory device includes a second bit line extending along the direction. In one aspect, the memory device includes a switch coupled between the first bit line and the second bit line.

Memory device including separate negative bit line

A method of performing an in-memory computation includes storing a first subset of data in a first segment of a first memory array and a second subset of the data in a second segment of the first memory array, latching a first data bit from a first column of memory cells in the first segment of the first memory array, sequentially reading a plurality of second data bits from a second column of memory cells in the second segment of the first memory array, and performing a logic operation on each combination of the latched first data bit and each second data bit.

Memory computation method

A circuit includes a data register configured to receive and output successive data elements of a plurality of data elements responsive to a clock signal, wherein each data element of the plurality of data elements includes a total number of bits N. A signal generation portion is configured to output a first selection signal responsive to the clock signal, the first selection signal includes two alternating sequences, values of the first sequence increment from zero to N−1, and values of the second sequence decrement from N−1 to zero. A selection circuit coupled to the data register is configured to output the N bits of each data element of the plurality of data elements in a first sequential order responsive to the first sequence of the first selection signal, and in a second sequential order opposite the first sequential order responsive to the second sequence of the first selection signal.

Data sequencing circuit and method

A memory device includes a first bit cell, a second bit cell, a first word line and a second word line. A first boundary of the second bit cell is adjacent with a first boundary of the first bit cell. The first word line is coupled to the first bit cell. The second word line is coupled to the second bit cell. A first segment of the first word line is overlapped with the first boundary of the second bit cell in a plan view, and a first segment of the second word line is overlapped with a second boundary of the second bit cell in the plan view.

Memory device

A memory device and a method for operating the memory device are provided. The memory device includes a memory cell and a bit line connected to the memory cell. A negative voltage generator is connected to the bit line. The negative voltage generator, when enabled, is operative to provide a first write path for the bit line. A control circuit is connected to the negative voltage generator and the bit line. The control circuit is operative to provide a second write path for the bit line when the negative voltage generator is not enabled.

Memory device having a negative voltage circuit

Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

Voltage regulator with power rail tracking

An SRAM includes multiple memory cells, each memory cell includes a data storage unit; a data I/O control adapted to input data to, and output data from, a data line; and multiple access controls respectively connected to at least two access control lines (WL's) and adapted to enable and disable the data input and output from the at least two WL's. The access controls are configured to permit data input only when both WL's are in their respective states that permit data input. A method of writing to a group of SRAM cells include sending a first write-enable signal to the cells via a first WL, sending a group of respective second write-enable signals to the respective cells, and, for each of the cells, preventing writing data to the cell if either of the first write-enable signal and respective second write enable signal is in a disable-state.

Bitcell supporting bit-write-mask function

An integrated circuit (IC) die includes first through third adjacent rows of through-silicon vias (TSVs), and first and second adjacent rows of memory macros. TSVs of the first row of TSVs extend through and are electrically isolated from memory macros of the first row of memory macros. TSVs of the third row of TSVs extend through and are electrically isolated from memory macros of the second row of memory macros.

Integrated circuit die with memory macro including through-silicon via and method of forming the same

A memory device is provided. The memory device includes a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. A first column of the plurality of columns of the matrix includes a first plurality of memory cells of the plurality of memory cells, a first pair of bit lines connected to each of the first plurality of bit cells, and a second pair of bit lines connectable to the first pair of bit lines through a plurality of switches.

Memory device with additional write bit lines

A memory array is disclosed. The memory array includes a plurality of memory cells disposed over a substrate. Each of the memory cells is coupled to a corresponding one of a plurality of word lines and a corresponding one of a plurality of bit line pairs. First four of the memory cells that are coupled to four consecutive ones of the word lines and to a first one of the bit line pairs are abutted to one another on the substrate along a single lateral direction.

Memory devices with improved bit line loading

A memory device includes a memory array having a first memory cell in a first column of the memory array, a second memory cell in the first column of the memory array, a first read bit line extending in a column direction and connected to the first memory cell to read data from the first memory cell, and a second read bit line extending in the column direction and connected to the second memory cell to read data from the second memory cell.

Separated read BL scheme in 3T dram for read speed improvement

A 3D IC structure includes multiple die layers, such as a top die layer and a bottom die layer. The top die layer and/or the bottom die layer each includes devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. The devices on the first and the second die layers are laterally surrounded by, or adjacent, vertical interconnect structures (VIS).

Vertical interconnect structures in three-dimensional integrated circuits

A device includes first and second gate electrodes, a word line and a first metal island. The first gate electrode corresponds to transistors of a memory cell. The second gate electrode is separated from the first gate electrode and corresponds to the transistors. The word line is coupled to the memory cell and located between the first and the second gate electrodes. The first metal island is configured to couple a first power supply to the memory cell. A first boundary of the first metal island is located between first and second boundaries of the first gate electrode and is located between first and second boundaries of the word line, and each of the first boundary of the first gate electrode and the first boundary of the word line is located between first and second boundaries of the first metal island.

SRAM cell word line structure with reduced RC effects

Growing community of inventors

Hsinchu, Taiwan

Hidehiro Fujiwara