Spansion Llc.

Other

Fasl LLC

Cypress Semiconductor Corporation

Advanced Micro Devices Corporation

Globalfoundries Inc.

Monterey Research, LLC

Advnaced Micro Devices, Inc.

Hidehiko Shiraiwa

Mark T Ramsbey

Jean Y Yang

Tazrien Kamal

Arvind Halliyal

Jaeyong Park

Lei Xue

Rinji Sugino

Yider Wu

Satoshi Torii

Minh Van Ngo

Mark W Randolph

Youseok Suh

Angela Tai Hui

Meng Ding

Harpreet Kaur Sachar

Emmanuil Lingunis

Shenqing Fang

Kuo-Tung Chang

Wei Zheng

Simon Siu-Sing Chan

Jean Yee-Mei Yang

Ching-Huang Lu

Simon S Chan

Joong Jeon

Amol Ramesh Joshi

Fred T K Cheung

Amir Hossein Jafarpour

Michael Allen Van Buskirk

Narbeh Derhacobian

Ravi S Sunkavalli

Chih-Yuh Yang

David Michael Rogers

Janet S Wang

David H Matsumoto

Lovejeet Singh

Yu Nan Sun

Scott Allan Bell

Masaru Yano

Hideki Arakawa

Kouros Ghandehari

Inkuk Kang

Tim Thurgate

Chuan Lin

Kenichi Ohtsuka

Bradley Marc Davis

Chi K Chang

Dawn M Hopper

Ning Cheng

Takashi Whitney Orimoto

Pei-Yuan Gao

Yun Wu

Hapreet Sachar

Jeffrey Allan Shields

Cyrus E Tabery

Darlene G Hamilton

Yi He

Che-Hoo Ng

Allison Holbrook

Yukio Hayakawa

Jayendra D Bhakta

Hirokazu Tokuno

Sung-Yong Chung

Cinti Xiaohua Chen

Gulzar Ahmed Kathawala

Weidong Qian

Hiroyuki Nansei

Edward Hsia

Michael Brennan

Boon-Yong Ang

Zubin Patel

Takayuki Maruyama

Alok Nandini Roy

Mark E Ramsbey

Ravi Sunkavalli

Janet Wang

Emmanuil Manos Lingunis

An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.

Non-volatile memory with silicided bit line contacts

A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

System and method for manufacturing self-aligned STI with single poly

An integrated circuit comprises a first poly-silicon region including a first poly-silicon layer, a second poly-silicon layer disposed over the first poly-silicon layer, a first poly-silicon finger associated with the first poly-silicon layer, and a second poly-silicon finger associated with the second poly-silicon layer. The first poly-silicon finger and the second poly-silicon finger are oriented in a substantially orthogonal manner relative to each other. The integrated circuit comprises a second poly-silicon gate region including the first poly-silicon layer. The first polysilicon gate region and the second polysilicon gate region each have different poly-silicon gate structures.

Integrating transistors with different poly-silicon heights on the same die

Methods and systems of fabricating a wordline protection structure are described. As described, the wordline protection structure includes a polysilicon structure formed adjacent to a memory core region. The polysilicon structure includes first doped region positioned on a core side of the polysilicon structure and a second doped region positioned on a spine side of the polysilicon structure. An un-doped region positioned between the first and second doped regions. A conductive layer is formed on top of the polysilicon structure and arranged so that it does not contact the un-doped region at either the transition between the first doped region and the un-doped region or the second doped region and un-doped region.

Leakage reducing writeline charge protection circuit

A shallow bipolar junction transistor comprising a high voltage n+ well implanted into a semiconductor substrate. The shallow bipolar junction transistor further comprises a bit line n+ implant (BNI) above the high voltage n+ well and an oxide nitride (ONO) layer above the high voltage n+ well. A portion of the ONO layer isolates the BNI from a shallow trench isolation (STI) region.

Shallow bipolar junction transistor

Non-Volatile memory with silicided bit line contacts

A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.

Memory cell system with multiple nitride layers

A method of manufacturing an integrated circuit is provided with a semiconductor substrate having a core region and a periphery region. A charge-trapping dielectric layer is deposited in the core region, and a gate dielectric layer is deposited in the periphery region. Bitlines are formed in the semiconductor substrate in the core region and not in the periphery region. A wordline-gate layer is formed and implanted with dopant in the core region and not in the periphery region. A wordline and gate are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate around the gate, and the gate is implanted with a gate doping implantation in the periphery region and not in the core region.

Memory manufacturing process with bitline isolation

A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.

Self-aligned STI with single poly for manufacturing a flash memory device

A method and manufacture for memory device fabrication is provided. Spacer formation and junction formation is performed on both: a memory cell region in a core section of a memory device in fabrication, and a high-voltage device region in a periphery section of the memory device in fabrication. The spacer formation and junction formation on both the memory cell region and the high-voltage device region includes performing a rapid thermal anneal. After performing the spacer formation and junction formation on both the memory cell region and the high-voltage device region, spacer formation and junction formation is performed on a low-voltage device region in the periphery section.

Method and manufacture for embedded flash to achieve high quality spacers for core and high voltage devices and low temperature spacers for high performance logic devices

Growing community of inventors

San Jose, CA, United States of America

Hidehiko Shiraiwa