Kabushiki Kaisha Toshiba

Hideaki Ninomiya

Tomoki Inoue

Tsuneo Ogura

Koichi Sugiyama

Masakazu Yamaguchi

Ichiro Omura

Tomoko Matsudai

Kazutoshi Nakamura

Yuichi Oshino

Yoshihiro Yamaguchi

Hiromichi Ohashi

Wolfgang Fichtner

Kenichi Matsushita

Masahiro Tanaka

Shigeru Hasegawa

Yoshiko Ikeda

Satoshi Teramae

Naoya Yoshimura

A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Power semiconductor device

According to one embodiment, a semiconductor device comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a gate insulating layer, a fourth semiconductor region of the second conductivity type, a first conductive unit and a first insulating layer. The fourth semiconductor region is provided selectively on the first semiconductor region. The fourth semiconductor region is separated from the second semiconductor region. At least a portion of the first conductive unit is surrounded with the fourth semiconductor region. At least a portion of the first insulating layer is provided between the first conductive unit and the fourth semiconductor region. A thickness of a portion of the first insulating layer is thinner than a film thickness of the gate insulating layer.

Semiconductor device and method of manufacturing the same

A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a pair of conductive bodies, a third semiconductor layer of the second conductivity type, and a fourth semiconductor layer of the first conductivity type. The second semiconductor layer is provided on the first semiconductor layer on the first surface side. The pair of conductive bodies are provided via an insulating film in a pair of first trenches extending across the second semiconductor layer from a surface of the second semiconductor layer to the first semiconductor layer. The third semiconductor layer is selectively formed on the surface of the second semiconductor layer between the pair of conductive bodies and has a higher second conductivity type impurity concentration in a surface of the third semiconductor layer than the second semiconductor layer.

A collector layer of a first conductivity type is provided in the IGBT region and the boundary region and functions as a collector of the IGBT in the IGBT region. A cathode layer of a second conductivity type is provided in the diode region apart from the collector layer and functions as a cathode of the diode. A drift layer of the second conductivity type is provided in the IGBT region, the boundary region, and the diode region, the drift layer being provided on sides of the collector layer and the cathode layer opposite the first electrode. A diffusion layer of the first conductivity type is provided in the boundary region on a side of the drift layer opposite the first electrode.

Semiconductor device

In one embodiment, a semiconductor device includes a semiconductor substrate having first and second main surfaces, control electrodes disposed in trenches on the first main surface of the semiconductor substrate and extending in a first direction parallel to the first main surface, and control interconnects disposed on the first main surface of the semiconductor substrate and extending in a second direction perpendicular to the first direction. The semiconductor substrate includes a first semiconductor layer of a first conductivity type, second semiconductor layers of a second conductivity type on a surface of the first semiconductor layer on a first main surface side, third semiconductor layers of the first conductivity type disposed on surfaces of the second semiconductor layers on the first main surface side and extending in the second direction, and a fourth semiconductor layer of the second conductivity type on the second main surface of the semiconductor substrate.

Insulated gate bipolar transistor having control electrode disposed in trench

A semiconductor device comprises a first base layer of a first conductivity type; a plurality of second base layers of a second conductivity type, provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers, and formed to be deeper than the second base layers; an emitter layer formed along the trench on a surface of the second base layers; a collector layer of the second conductivity type, provided on a second surface of the first base layer opposite to the first surface; an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated from the second base layers and the emitter layer by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being deeper than the second base layers and being electrically isolated from the emitter layer and the second base layers.

A semiconductor device includes a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a trench formed from the surface of the barrier layer to such a depth as to reach a region in the vicinity of an interface between the barrier layer and the base layer, a gate electrode formed in the trench via a gate insulating film, a contact layer of a second conductivity type selectively formed in a surface portion of the barrier layer, a source layer of the first conductivity type selectively formed in the surface portion of the barrier layer so as to contact the contact layer and a side wall of the gate insulating film in the trench, and a first main electrode formed so as to contact the contact layer and the source layer.

A semiconductor device including a base layer of a first conductivity type having a first main surface and a second main surface opposite the first main surface, a first main electrode layer connected to the first main surface, control regions arranged inside grooves penetrating the first main electrode layer and reach inside the base layer, and a second main electrode layer of the first conductivity type and connected to the second main surface.

Semiconductor device having rectifying action

A semiconductor device disclosed herein comprises: a first base region which is of a first conductivity type; a second base region which is of a second conductivity type and which is selectively formed on a major surface of the first base region; a stopper region which is of a first conductivity type and which is formed on the major surface of the first base region, the stopper region being a predetermined distance away from the second base region and surrounding the second base region; and a ring region which is of a second conductivity type which is formed on the major surface of the first base region between the second base region and the stopper region, the ring region being spirally around the second base region and electrically connected to the second base region and the stopper region.

Semiconductor device and junction termination structure

A semiconductor device comprises a first base layer of a first conductive type which has a first surface and a second surface; a second base layer of a second conductive type which is formed on the first surface; first and second gate electrodes which are formed by embedding an electrically conductive material into a plurality of trenches via gate insulating films, the plurality of trenches being formed such that bottoms of the trenches reach the first base layer; source layers of the first conductive type which are formed on a surface area of the second base layer so as to be adjacent to both side walls of the trench provided with the first gate electrode and one side wall of the trench provided with the second gate electrode, respectively; an emitter layer of the second conductive type which is formed on the second surface; emitter electrodes which are formed on the second base layer and the source layers; a collector electrode which is formed on the emitter layer; and first and second terminals which are electrically connected to the first and second gate electrodes, respectively.

This disclosure concerns a semiconductor device that includes a first base layer; second base layers provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers; an emitter layer formed on a surface of the second base layers; a collector layer provided below a second surface of the first base layer, an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being electrically isolated from the emitter layer and the second base layers, wherein the space section includes a semiconductor layer being deeper than the second base layers.

An insulated gate semiconductor device, includes an isolating structure shaped in a circulating section along the periphery of a semiconductor substrate to isolate that part from an inside device region, a peripheral diffusion region of the semiconductor substrate located outside the isolating structure, a plurality of cell structures defined in the inside device region and divided in segments by insulated trench-shaped gates to have a base region covered with an emitter region in its upper surface, a collector region, and an emitter electrode electrically connected to the emitter region and the base region, a dummy base region contiguous to the cell structures and configured as a base region that has its upper surface left without the emitter region connected to the emitter electrode, an inner region defined in and insulated from the dummy base region, and a connection part to electrically connect the inner region to the emitter electrode.

Growing community of inventors

Kanagawa, Japan

Hideaki Ninomiya