Fujitsu Corporation

Hideaki Isogai

Isao Fukushi

Kouichi Kitano

Katsuyuki Yamada

Miki Tanaka

A semiconductor memory device used as a bipolar random access memory including a plurality of pairs of word lines, a plurality of pairs of bit lines, and a plurality of static memory cells located at the intersections of and connected between the pairs of word and bit lines. A plurality of constant current sources are selectively connected to the bit lines. A reading-writing voltage control circuit controls the potential of each bit line during the reading and writing of data and a writing current control circuit controls the current flowing to each bit line during the writing of data into the memory cell. Further, the writing current control circuit connects the constant current source to the reading-writing voltage control circuit in the writing of data to the memory cell. Accordingly, the bipolar random access memory can operate at a high speed with reduced power consumption and without unnecessary current flowing in the peripheral circuits.

Bipolar random access memory

A semiconductor memory circuit including a charge absorbing circuit. The charge absorbing circuit absorbs at least a current induced by a voltage increase in the word line occurring soon after the word line is switched from a selection state to a nonselection state.

Semiconductor memory with word line charge absorbing circuit

A semiconductor memory device including static memory cells connected at intersections of word lines and pairs of bit lines, in which writing is carried out by changing the potentials of the paired bit lines according to writing data of binary digits '1' and '0' and turning on one transistor of a memory cell while turning off the other transistor of the cell. A characteristic feature of the invention is that, according to the write data, one of the paired bit lines is maintained at a low level while the other bit line is simultaneously maintained at a high level, and the period of maintenance of the high level is shorter than the period of maintenance of the low level.

Circuit and method for writing in a semiconductor memory device

A static semiconductor memory device comprises static memory cells respectively connected to a pair of word lines, and a pair of diodes. One end of each diode is connected to a corresponding one of the pair of bit lines, so as to absorb the electric currents from the bit lines, and the other end of each diode is commonly connected to a constant current source via a transistor which is controlled together with column-selecting transistors according to a column-selecting signal.

Static semiconductor memory device

This invention relates to a bipolar static type semiconductor memory device which reduces the influence of disturbances on the memory cells of non-selected chips and thereby obtains a large memory holding margin for the memory cells. The semiconductor memory device of the present invention comprises flip-flop type circuit memory cells at the intersecting points of word lines and bit lines. The memory holding margin of the memory cells is increased by clamping the bit line voltage of the non-selected cells to a voltage higher than the bit line voltage of a selected chip being read.

Bipolar static semiconductor memory device with a high cell holding

A decoder circuit comprises input gates, a logic circuit for generating an output according to input signals, an output gate for driving a word line, and a current control device for activating the output gate according to the output of the logic circuit.

Decoder circuit

A decoder circuit for a semiconductor memory device includes a plurality of input terminal gates for receiving address signal bits and for producing the same signal as well as inverted signals thereof; first decoder lines for decoding output signals of some of the input terminal gates; and diode matrices or multi-emitter transistors of which one terminal is connected to any decoder line selected from the first decoder lines, and of which another terminal is connected via a resistor to a power source and to the base of transistors which drive a group of output terminal gates. The diode matrices or multi-emitter transistors being capable of turning the transistor on or off depending upon the potential of the first decoder lines. The decoder circuit provides second decoder lines to which are connected constant current sources; emitter follower-connected transistors which are inserted between the power source and the second decoder lines, and which are turned on or off by the output signals of the remainder of the input terminal gates; and diode matrices or multi-emitter transistors of which one terminal is connected to any decoder line selected from the second decoder lines, and of which another terminal is connected via a resistor to the emitter of the transistor for driving the group of the output terminal gates and to the base of an output transistor. The diode matrices or the multi-emitter transistors being capable of turning the output transistor on or off depending upon the potential of the second decoder lines and upon the emitter potential of the transistor which drives the group of the output terminal gates.

A semiconductor memory device including memory cells, formed by a pair of multi-emitter transistors each having a collector and a base which are cross connected to each other and arranged in row and column directions, and read-out transistors, each having an emitter which is commonly connected to one of the emitters of the multi-emitter transistors, wherein the read-out transistors are arranged in each column. The multi-emitter transistors and the read out transistors are formed in patterns and the characteristics of both the multi-emitter and read-out transistors have the same variation due to a dispersion of the patterns caused by the manufacturing process.

Semiconductor memory device

A decoder circuit comprises a differential amplifier circuit which receives one or a plurality of line selection signals which are to be decoded, switching circuits for switching predetermined lines to in high or low level states according to the output signal supplied from the differential amplifier circuit, and constant current supplying circuits for supplying constant current to the predetermined lines according to the signal supplied from the switching circuits. The switching circuits are connected in parallel with respect to the constant current supplying circuits.

A decoder circuit which receives a plurality of address signals and selects one of the n.times.m word lines for driving a semiconductor memory device. The decoder circuit includes a high level selection circuit which receives the upper address signals and produces n outputs, one of the n outputs is selected to be a high level, while the other (n-1) outputs are rendered at a low level. The decoder circuit also includes a low level selection circuit which receives the lower address signals and produces m outputs, one of the m outputs is selected to be the low level, while the other (m-1) outputs are rendered at the high level. The decoder circuit additionally includes n.times.m coupling circuits each of which receives one output from the high level selection circuit and one output from the low level selection circuit and which corresponds to one of the n.times.m word lines. Each of the coupling circuit selects the corresponding word line when the high level output from the high level selection circuit and the low level output from the low level selection circuit are simultaneously applied to the coupling circuit.

A semiconductor memory circuit, comprising memory cells; word lines, hold lines and bit lines connected to respective memory cells; and a hold-current controlling circuit. The hold-current controlling circuit comprises identical controlling circuit elements connected to respective hold lines and a constant-current source commonly connected to the controlling circuit elements. Each of the controlling circuit elements comprises means for absorbing electric charges from respective hold lines, when corresponding word lines change from a selection status to a non-selection status, until the voltage level of the hold line reaches a full 'L' or 'H' level, and means for blocking a flow of electric charges from the hold line, when a corresponding word line changes from a non-selection status to a selection status, during a predetermined interval after time data switching from one memory cell to another memory cell is performed.

Semiconductor memory circuit

In an electronic circuit of a current switch construction in which the emitters of a first transistor and a second transistor are commonly connected to a constant-current supply, and a load resistor is connected to the collector of the first transistor, thereby to take out an output from the collector, the improvement being a pnp-type transistor, in which temporarily flows an electric current to a collector circuit of the first transistor when it is rendered non-conductive, which is inserted in a collector circuit of the second transistor.

Electronic circuit

A word driver in a decoder circuit of a semiconductor device has either a matrix of diodes or a multi-emitter transistor, each of said diodes or emitters of said multi-emitter transistor being connected between one of the decoder lines and a junction of a resistor circuit which is connected to a power source and another transistor which is connected to one of the word lines.

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Higashikurume, Japan

Hideaki Isogai