Samsung Electronics Co., Ltd.

Heung-Soo Im

June Hyung Lee

Oh-Suk Kwon

Dong-Woo Lee

Hyong-Gon Lee

Young-Ho Lim

Dae-Seok Byeon

Dong-Hyuk Chae

Kang-Deog Suh

Sang-Ki Hwang

Yong-Seok Seo

Sun-Mi Choi

A nonvolatile memory device and programming method and apparatus therefore are described that include operatively coupled first and second sense amplifiers having first and second data registers or latches, a storage circuit for storing a data of the second amplifier, a pass/fail check circuit for checking the content of the second data register whether a cell of the memory device has been sufficiently programmed and a restore circuit for resetting the second data register for reprogramming the device until sufficiently programmed.

Memory devices with page buffer having dual registers and method of using the same

Embodiments of the invention provide a multi-chip system that includes a first and a second semiconductor memory device. The memory devices are mounted in a single package. The multi-chip system has a continuous burst read mode of operation, in which a read operation can be successively carried out without latency even though an address region moves from the first semiconductor memory device to the second memory device.

Multi-chip system having a continuous burst read mode of operation

Disclosed is a nonvolatile semiconductor memory device having selective multiple-speed operation modes selected by simple options. The nonvolatile semiconductor memory device includes a memory cell array formed of a plurality of cell array blocks each having a plurality of cell strings, the cell string formed with floating gate memory cell transistors such that their control gates each are respectively connected to a plurality of word lines, and its drain-source channels are series connected to each other between a string select transistor and a ground select transistor. The memory device also includes a multiple-speed mode option part for generating a multiple-speed option signal, and an addressing circuit for selecting a page size and block size of the memory cell array different from one another in response to a state of the multiple-speed option signal.

Nonvolatile semiconductor memory device having selective multiple-speed operation mode

A memory device has an array of memory cells to store data, and a Y-gating circuit to gate data stored in a group of the memory cells. A page buffer is coupled between the memory cell array and the Y-gating circuit. The page buffer includes a dual register corresponding to each memory cell of the group. The dual register includes a first register and an associated second register. The first and second registers are adapted to exchange data with each other, with cells of the memory cell array, and with the Y-gating circuit.

Nonvolatile memory device with page buffer having dual registers and methods of using the same

A semiconductor memory device is provided, which includes a chip enable buffer and an address buffer. The chip enable buffer generates first and second control signals having opposite phases of logic, the first and second control signals enable and disable operations of the semiconductor memory device, respectively. The address buffer includes an input terminal, and a blocking terminal connected to the input terminal, the input terminal receiving an external address signal under control of the first control signal, and the blocking terminal generating an address signal in response to the second control signal. The address buffer further includes a shift detecting circuit connected to the blocking terminal for generating first and second short pulses by detecting shift of the address signal, wherein the pluses are used as signals for reading data of the semiconductor memory device.

Semiconductor memory device having noise tolerant input buffer

Disclosed is a non-volatile semiconductor memory device provided therein.with a word line defect check circuit. The non-volatile semiconductor memory device includes: a memory cell array including a plurality of cell array blocks including a plurality of cell strings that consist of floating gate memory cell transistors that its drain-source channels are in series connected each other between string select transistors and ground select transistors and that its control gates are correspondingly connected to a plurality of word lines, and a word line short check circuit that inputs different levels of voltage to each of the plurality of word lines that is adjacent from one another during a predetermined charging time, and that generates a short sense signal that indicates whether short between adjacent word lines is occurred by checking voltage levels of the word lines that were supplied with a same level of voltage, after the charging time is lapsed by a predetermined time.

Non-volatile semiconductor memory device having word line defect check circuit

A sense amplifier circuit includes a first voltage-controlled current source to supply current proportional to a first bias voltage to a reference node and a second voltage-controlled current source to supply current proportional to a second bias voltage to a sensing node. The first and second bias voltages are internally generated in response to an externally applied sense amp control signal. A current mirror circuit is also provided for the sense amplifier circuit. The current mirror circuit commonly deliver current proportional to the voltage level of the reference node to the reference and sensing nodes. A differential amplifier amplifies a difference voltage between reference and sensing nodes. This current mirror type sense amplifier circuit allows data sensing operation to be performed without being influenced from the external conditions and without sensing speed loss due to the instability of the precharge current since the voltage-controlled current sources are controlled by the internal bias voltages.

Current mirror type sense amplifier circuits for semiconductor memory devices and methods of operating same

Disclosed herein is a sense amplifier circuit which includes a first, a second and a third similar load transistors. The first and second load transistors supply a dummy data line with a current of the same amount to one another. Acting in a current mirror configuration, the third load transistor supplies a data line with a current equaling the total current supplied by the first and second load transistors. A dummy memory cell is composed of the same transistor as an on-state memory cell. According to this sense amplifier structure, it is very easy to obtain a dummy cell current which has an intermediate value consistently between an on cell current and an off cell current of the memory cell, which are supplied from the third load transistor to the data line. The improved intermediate value yields a reliable readout of the memory cell.

Sense amplifier circuit for use in a semiconductor memory device

Disclosed is a nonvolatile semiconductor memory device which comprises a mode register for storing the data for controlling plural operating modes, for instance, the RAS and the CAS latency, the burst length, and the burst type, of the memory device. The mode register of the present invention comprises a plurality of programmable elements, and a default value of the mode register is set depending on whether or the programmable elements are programmed. Furthermore, each of the programmable elements is comprised of the same element as the memory cells of the memory device. With the present invention, various default values for the mode register are set in accordance with the user's requirement without an additional process step.

Programmable mode register for use in synchronized memory device

Current mirror type sense amplifier circuit for semiconductor memory

A mask ROM of the invention discharges bit lines selectively before a bit line precharge operation in response to an externally applied command. A column decoder selects one of bit lines in response to column select signals. A discharge control circuit generates a first discharge control signal in response to the command. A discharge predecoder generates a plurality of second discharge control signals by logically combining the first discharge control signal with the column select signals. A bit line discharge circuit selectively discharges the bit lines in response to the second discharge control signals. The mask ROM is free from bit line coupling due to the selection of particular memory cells, the cell selection sequence and the programmed states of the selected cells, leading to an improvement in read speed.

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Kyungkido, South Korea

Heung-Soo Im