Hynix Semiconductor Inc.

Hyundai Electronics Industries Co. Ltd.

Heung Jae Cho

Kwan Yong Lim

Dae Gyu Park

Yong Soo Kim

Moon Sig Joo

Se Aug Jang

Won Joon Choi

Seung Ho Pyi

Jung Ho Lee

In Seok Yeo

Kwon Hong

Tae Kyun Kim

Ki Seon Park

Hong Seon Yang

Sung Jin Whang

Tae Ho Cha

Min Gyu Sung

Tae Hang Ahn

Yong Top Kim

Jin Sang Park

Dea Gyu Park

Tae Yoon Kim

Seung Ryong Lee

A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.

Semiconductor device with bulb-type recessed channel and method for fabricating the same

A method of fabricating a non-volatile memory device includes: forming a tunnel insulation layer pattern and a floating gate electrode layer pattern over a semiconductor substrate; forming an isolation trench by etching an exposed portion of the semiconductor substrate so that the isolation trench is aligned with the tunnel insulation layer pattern and the floating gate electrode layer pattern; forming an isolation layer by filling the isolation trench with a filling insulation layer; forming a hafnium-rich hafnium silicon oxide layer over the isolation layer and the floating gate electrode layer pattern; forming a hafnium-rich hafnium silicon oxynitride layer by carrying out a first nitridation on the hafnium-rich hafnium silicon oxide layer; forming a silicon-rich hafnium silicon oxide layer over the hafnium-rich hafnium silicon oxynitride layer; forming a silicon-rich hafnium silicon oxynitride layer by carrying out a second nitridation on the silicon-rich hafnium silicon oxide layer; and forming a control gate electrode layer over the silicon-rich hafnium silicon oxynitride layer.

Method of fabricating non-volatile memory device

A method of fabricating a non-volatile memory device having a charge trapping layer includes forming a tunneling layer, a charge trapping layer, a blocking layer and a control gate electrode layer over a substrate, forming a mask layer pattern on the control gate electrode layer, performing an etching process using the mask layer pattern as an etching mask to remove an exposed portion of the control gate electrode layer, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness, forming an insulating layer for blocking charges from moving on the control gate electrode layer and the mask layer pattern, performing anisotropic etching on the insulating layer to form an insulating layer pattern on a sidewall of the control gate electrode layer and a partial upper sidewall of the blocking layer, and performing an etching process on the blocking layer exposed by the anisotropic etching, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness.

Method of fabricating non-volatile memory device having charge trapping layer

A method for manufacturing a non-volatile memory device having a charge trap layer comprises in one embodiment: forming a first dielectric layer over a semiconductor substrate; forming a second dielectric layer having a higher dielectric constant than that of the first dielectric layer over the first dielectric layer; forming a nitride buffer layer for preventing an interfacial reaction over the second dielectric layer; forming a third dielectric layer by supplying a radical oxidation source onto the nitride buffer layer to oxidize the nitride buffer layer, thereby forming a tunneling layer comprising the first, second, and third dielectric layers; and forming a charge trap layer, a shielding layer, and a control gate electrode layer over the tunneling layer.

Method for manufacturing non-volatile memory device having charge trap layer

Disclosed are a semiconductor devices and method of fabricating the same. Anti-etch films are formed in the top corners of the device isolation film using a material that has a different etch selectivity ratio from nitride or oxide and is not etched in an oxide gate pre-cleaning process. It is thus possible to prevent formation of a moat at the top corners of the device isolation film and the gate oxide film from being thinly formed, thereby improving reliability and electrical characteristics of the device.

Semiconductor device and a method of manufacturing the same

A method for forming a metal gate capable of preventing degradation in a characteristic of a gate insulating film upon formation of the metal gate. The method of forming the metal gate comprises the steps of providing a silicon substrate having device isolation films of a trench shape for defining an active region; forming a gate insulating film on the surface of the silicon substrate by means of a thermal oxidization process; sequentially forming a barrier metal film and a metal film for the gate on the gate insulating film; and patterning the metal film for the gate, the barrier metal film and the gate insulating film, wherein deposition of the barrier metal film and the metal film for the gate is performed by means of an atomic layer deposition (ALD) process or remote plasma chemical vapor deposition (CVD) process.

Method of forming a metal gate in a semiconductor device using atomic layer deposition process

Disclosed is the method of forming the gate in the semiconductor device. The present method can prevent abnormal oxidization and lifting at the interface of the stack gate consisting of polysilicon and a metal and can be applied to even the single metal gate, by replacing a re-oxidization process for recovering damage of the gate oxide film generated in the gate patterning process with the oxygen plasma treatment.

Method of forming gates in semiconductor devices

The present invention discloses the single gate CMOS with the surface channel manufactured according to the manufacturing method of the present invention is very advantageous for improving the characteristics, yield and reliability of the device, by performing decoupled plasma nitridation (DPN) process on the gate oxide film of the cell NMOS and the peripheral PMOS, respectively, thereby forming a silicon nitride on the surface of the gate oxide film. Further, the single gate CMOS with the surface channel can be formed more easily through the simplified process in overall, without requiring a separate transient ion implantation process, even when the gate electrode of the n polysilicon layer is used, by having the threshold voltage of the cell NMOS be approximately &plus;0.9V, the threshold voltage of the peripheral PMOS be approximately &minus;0.5V and above, and the threshold voltage of the peripheral NMOS be approximately &plus;0.5V and below. In addition, since the cell NMOS already has &plus;0.9V of threshold voltage, back bias does not have to be applied separately to achieve the &plus;0.9V threshold voltage, and the device with low power consumption is formed successfully.

CMOS of semiconductor device and method for manufacturing the same

CMOS device arrangements have a surface channel, and a method for manufacturing the same by forming a multi-layer that includes a first metal layer, a polysilicon layer and a second metal layer having a work function from 4.8 through 5.0 eV on a cell region NMOS and a gate electrode of a peripheral circuit region PMOS, and by forming a multi-layer that includes a polysilicon layer and a second metal layer on a gate electrode of a peripheral circuit region NMOS. Because of the multi-layered gate electrode, a separate transient ion implantation process is not necessary, which consequently simplified the CMOS manufacturing process, while maintaining the threshold voltage of each peripheral circuit region &minus;0.5V and below, and the threshold voltage of the peripheral circuit region NMOS &plus;0.5V and below. Meantime, since the cell NMOS has the threshold voltage of &plus;1V thanks to the first metal layer, no separate back bias is necessary, thereby forming a device with low power consumption, which consequently improves characteristics, yield and reliability of the device.

Cmos of semiconductor device and method for manufacturing the same

A semiconductor device and a method for fabricating the semiconductor device using a damascene process are disclosed. The method includes forming an Al O film over a dummy gate disposed over a semiconductor substrate. Next, the dummy gate and a portion of the Al O film are removed to form a groove defined by remains of the Al O film and the semiconductor substrate. Then, a subsequent film is deposited within the groove, and a gate material is formed over the second film to complete the semiconductor device.

Semiconductor device and method for fabricating the same using damascene process

A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (Ti Al ) N film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a nMOS region, a (Ti Al ) N film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.

Method of manufacturing semiconductor devices with titanium aluminum nitride work function

The present invention discloses a method for forming a gate for semiconductor devices by depositing a TaO N film as a gate oxide film. The method includes the steps of providing a semiconductor substrate where a device isolation film has been formed, growing an SiO or SiON film on the semiconductor substrate, depositing an amorphous TaO N film on the SiO or SiON film, performing a low temperature annealing process to improve quality of the amorphous TaO N film, performing a high temperature annealing process ex-situ to remove organic substances and nitrogen in the amorphous TaO N film, and crystallize the amorphous TaO N film, and depositing a metal barrier film on the crystallized TaO N film, and depositing a polysilicon film or metal film for a gate electrode on the metal barrier film.

Growing community of inventors

Kyoungki-do, South Korea

Heung Jae Cho