Imec

Other

Interuniversitair Microelektronica Centrum (Imec)

Applied Materials, Inc.

Herbert Struyf

Serge Vanhaelemeersch

Werner Boullart

Ricardo Alves Donaton

Karen Irma Maex

Marleen Van Hove

Marc Schaekers

Jan Van Olmen

Joke Van Aelst

Dirk Hendrickx

Michael Baklanov

Kristel Van Baekel

Christian Jehoul

Karen A Maex

Michael R Baklanov

Ricardo Donaton

A method for patterning high aspect ratio vias is provided. More specifically a dry etching method is provided for patterning deep vias or vias with high aspects ratios thereby eliminating the hard mask undercut. A method is provided to create (pattern) deep vias in a substrate for use in three dimensional stacked semiconductor devices and/or structures. More specifically, a method is provided for patterning deep vias with an aspect ratio up to 10 into a Si substrate with smooth via sidewalls and sufficient slope to enable metallization.

High aspect ratio via etch

A method for patterning a dual damascene structure in a semiconductor substrate is disclosed. The patterning is a metal hardmask based pattering eliminating at least resist poisoning and further avoiding or at least minimizing low-k damage. The method can be used as a full-via-first patterning method or a partial-via-first patterning method.

Dual damascene patterning method

A method for anisotropic plasma etching of organic-containing insulating layers is disclosed. According to this method at least one opening is created in an organic-containing insulating layer formed on a substrate. These openings are created substantially without depositing etch residues by plasma etching said insulating layer in a reaction chamber containing a gaseous mixture which is composed such that the plasma etching is highly anisotropic. Examples of such gaseous mixtures are a gaseous mixture comprising a fluorine-containing gas and an inert gas, or a gaseous mixture comprising an oxygen-containing gas and an inert gas, or a gaseous mixture comprising HBr and an additive. The plasma etching of the organic-containing insulating layer can be performed using a patterned bilayer as an etch mask, said bilayer comprising a hard mask layer, being formed on said organic-containing insulating layer, and a resist layer being formed on said hard mask layer. A method is disclosed for forming a layer, protecting exposed surfaces of low-k dielectrics. More particularly the method comprises the steps of sealing exposed surfaces of a, preferably porous, low-k dielectric, by forming a protective layer on exposed surfaces during or after the step of patterning openings in the porous dielectric layers. Preferably this protective layer is formed by a N2/O2 plasma treatment of the exposed surfaces.

Anisotropic etching of organic-containing insulating layers

The present invention concerns a method for stripping the photoresist layer and the crust from a semiconductor. The crust has been formed with as a result of an ion implantation step, wherein the method comprises an ion assisted plasma step using a mixture of water vapour, helium and a F-containing compound in which radicals are generated, and the step of contacting said photoresist layer and crust with said radicals to remove said photoresist layer and crust from said semiconductor surface. Said plasma step is preferably an ion assisted plasma step.

Method for stripping ion implanted photoresist layer

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Kontich, Belgium

Herbert Struyf