Credence Systems Corporation

Henry Y Pun

Jeffrey D Currin

Michael R Ferland

In an integrated circuit tester module, pin electronics circuitry supplies leakage current to a circuit node which is connected to a signal pin of a device under test. The leakage current is compensated by connecting the circuit node to a voltage source at a first potential level, supplying current to the circuit node from a second potential level, and measuring current supplied to the circuit node from the voltage source. The second potential level is selectively varied in a manner such as to reduce the current supplied from the voltage source substantially to zero. The circuit node is then disconnected from the voltage source.

Integrated circuit tester with compensation for leakage current

Current consumption of a device under test (DUT) is measured using a tester including a device power supply (DPS) having force and return lines terminating in respective power supply terminals. The DUT is removably received by a load board having contact elements which are in electrically conductive pressure contact with the power supply terminals of the force and return lines and are connected to power supply pins of the DUT. A circuit branch including a bypass capacitor and an nMOSFET is connected between the force and return lines.

Integrated circuit tester with test head including regulating capacitor

An integrated circuit tester includes a quasi-autonomous test instrument for performing an acquisition task. The test instrument includes a state machine, a command stack for storing commands which specify parameters of the acquisition task, an acquisition device having at least one terminal for connection to a pin of the DUT for acquiring a value of a variable from the DUT in accordance with the defined parameters of the acquisition task, and an acquisition memory for temporarily storing acquired values and making the acquired values available after the test. The state machine is responsive to an externally supplied trigger to initiate performance of the acquisition task under control of a clock signal by reading a command from the command stack and to perform the acquisition task in accordance with the parameters specified in the command.

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Santa Clara, CA, United States of America

Henry Y Pun