International Business Machines Corporation

Globalfoundries Inc.

Infineon Technologies Ag

Samsung Electronics Co., Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Stmicroelectronics Gmbh

Infineon Technologies North America Corp.

Kabushiki Kaisha Toshiba

Henry K Utomo

Judson Robert Holt

Reinaldo Ariel Vega

Kangguo Cheng

Ravikumar Ramachandran

Yue Ke

Huiling Shang

Eric C Harley

Jin-Ping Han

Ramachandra Divakaruni

Huajie Chen

Rishikesh Krishnan

Keith Howard Tabakman

Daniel C Edelstein

Dureseti Chidambarrao

Yann A Astier

David Esteban

Ali Khakifirooz

Veeraraghavan S Basker

Haining S Yang

Werner A Rausch

Ying Li

Chung Woh Lai

Kern Rim

Dominic Joseph Schepis

Arvind Kumar

Eugene John O'Sullivan

Anthony J Annunziata

Thomas W Dyer

Anthony I Chou

Siddhartha Panda

Myung-Hee Na

Jong Ho Yang

Sang-Hyun Oh

Alexander Reznicek

Chih-Chao Yang

Bruce Bennett Doris

Theodorus E Standaert

Yun Yu Wang

Dechao Guo

Zhijiong Luo

Tsutomu Sato

Emre Alptekin

Rajendran Krishnasamy

Nathan P Marchack

Nivo Rovedo

Sameer Hemchand Jain

Ricky S Amos

Kevin K Chan

Terence B Hook

Shyue Seng Tan

Chengwen Pei

Michael Patrick Chudzik

Thomas N Adam

Renee Tong Mo

Unoh Kwon

Hiroyuki Miyazoe

Rajasekhar Venigalla

Yun-Yu Wang

Viraj Yashawant Sardesai

Abhishek Dube

Zhibin Ren

Jin-bum Kim

Jae Gon Lee

Pietro Montanini

Cung D Tran

Lee Wee Teo

Robert J Purtell

Christopher D Sheraw

Dan Mihai Mocuta

Michael Abramovich Gribelyuk

Paul Andrew Ronsheim

O Sung Kwon

Matthew W Stoker

Taek-Soo Jeon

Melissa Alyson Smith

Woo-Hyeong Lee

Shailendra Mishra

Richard J Murphy

Eric C T Harley

Wing L Lai

Richard O Henry

Tae-Ho Cha

Raymond Joy

Benjamin G Moser

Hyung-rae Lee

Kyung-Bum Koo

Yinxiao Yang

Ryan Matthew Mitchell

Yong Siang Tan

Oh Jung Kwon

Matthew Peter Sagianis

Eric T Harley

Luxherta Buzi

Marta Mottura

Bei Liu

Gerald L Leake

Dimitri Anastassios Levedakis

A method of fabricating a resistive semiconductor memory structure that provides in-situ selective etch of phase change materials during deposition of dielectric at low temperature (in the same chamber). The method provides, to a single processing chamber, a semiconductor wafer including a trimmed resistive memory device structure having one or more layers of phase change material used to form a resistive memory device. The one or more layers of phase change material have oxidized sidewall surfaces as a result of a prior etching step where a whole stack structure of the layers forming the resistive memory structure is etched. Then, an encapsulating of the trimmed resistive memory device structure is performed by depositing, within the processing chamber, using a PECVD, a layer of dielectric material, and during the encapsulating, etching, within the processing chamber, the wafer to selectively remove the phase change material oxidation at the sidewall surfaces.

In-situ low temperature dielectric deposition and selective trim of phase change materials

A device for isolating a microbe or a virion includes a semiconductor substrate; and a trench formed in the semiconductor substrate and extending from a surface of the semiconductor substrate to a region within the semiconductor substrate; wherein the trench has dimensions such that the microbe or the virion is trapped within the trench.

Semiconductor manufactured nano-structures for microbe or virus trapping or destruction

A device and method for forming a semiconductor device includes forming a gate structure on a channel region of fin structures and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

A shallow trench isolation layer is formed on a structure comprising semiconductor fins. Portions of the fins are recessed to a level below the shallow trench isolation layer. Epitaxial stressor regions are then formed on the recessed fin areas. A bottom portion of the epitaxial stressor regions are contained by the shallow trench isolation layer, which delays formation of the diamond shape as the epitaxial region is grown. Once the epitaxial stressor regions exceed the level of the shallow trench isolation layer, the diamond shape starts to form. The result of delaying the start of the diamond growth pattern is that the epitaxial regions are narrower for a given fin height. This allows for taller fins, which provide more current handling capacity, while the narrower epitaxial stressor regions enable a smaller fin pitch, allowing for increased circuit density.

Embedded source/drain structure for tall FinFet and method of formation

Back end of line (BEOL) metallization structures and methods generally includes forming a landing pad on an interconnect structure. A multilayer structure including layers of metals and at least one insulating layer are provided on the structure and completely cover the landing pad. The landing pad is a metal-filled via and has a width dimension that is smaller than the multilayer structure, or the multilayer structure and the underlying metal conductor in the interconnect structure. The landing pad metal-filled via can have a width dimension that is sub-lithographic.

Contact via structures

A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

A semiconductor structure is disclosed herein. The semiconductor structure includes two or more pillar structures disposed over a top surface of a substrate. The semiconductor structure further includes two or more contacts to the two or more pillar structures. The semiconductor structure further includes an insulator disposed between the two or more pillar structures and the two or more contacts. The two or more contacts are self-aligned to the two or more pillar structures.

Forming self-aligned contacts on pillar structures

A method of forming a semiconductor structure includes forming two or more pillar structures over a top surface of a substrate. The method also includes forming two or more contacts to the two or more pillar structures. The method further includes forming an insulator between the two or more pillar structures and the two or more contacts. The two or more contacts are self-aligned to the two or more pillar structures by forming the insulator via conformal deposition and etching the insulator selective to a spin-on material formed over the insulator between the two or more pillar structures.

Embedded source/drain structure for tall FinFET and method of formation

A method includes disposing a solution including a microbe or a virion on a surface of a semiconductor substrate, the semiconductor substrate having a trench extending from the surface to a region within the semiconductor substrate; wherein the the microbe or the virion is trapped within the trench of the semiconductor substrate.

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Newburgh, NY, United States of America

Henry K Utomo