Seagate Technology Incorporated

Other

Henry F Huang

Yiran Chen

Hai Li

Hongyue Liu

Wenzhong Zhu

Xiaobin Wang

Harry Hongyue Liu

Yong Lu

Haiwen Xi

Ran Wang

Dimitar Velikov Dimitrov

Kang Yong Kim

Hai (Helen) Li

KangYong Kim

Maroun Khoury

Andrew John Carter

Devices and methods for generating a random number that utilizes a magnetic tunnel junction are disclosed. An AC current source can be in electrical connection to a magnetic tunnel junction to provide an AC current to the magnetic tunnel junction. A read circuit can be used to determine a bit based on a state of the magnetic tunnel junction. A rate of production of the bits can be adjusted, such as by adjusting a frequency or amplitude of the AC current. A probability of obtaining a '0' or '1' bit can be managed, such as by an addition of DC biasing to the AC current.

Random bit generator that applies alternating current (AC) to magnetic tunnel junction to generate a random bit

A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The method also includes comparing the first bit line read voltage with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.

Spin-transfer torque memory self-reference read method

Various embodiments of the present invention are generally directed to a non-volatile resistive sense memory on-chip cache. In accordance with some embodiments, a processing circuit is formed on a first semiconductor substrate. A second semiconductor substrate is affixed to the first semiconductor substrate to form an encapsulated integrated chip package, wherein a non-volatile storage array of resistive sense memory (RSM) cells is formed on the second semiconductor substrate to cache data used by the processing circuit.

Non-volatile resistive sense memory on-chip cache

The present disclosure relates to methods of selectively placing a reference column or reference row in a memory array. The method includes measuring a resistance state resistance value for a plurality of variable resistive memory cells within a memory array and mapping a location of each measured variable resistive memory cell to form a map of the resistance state resistance values for a plurality of variable resistive memory cells within a memory array. Then a column or row is selected to be a reference column or reference row based on the map of the resistance state resistance value for a plurality of variable resistive memory cells within a memory array, to minimize read operation errors, and forming a variable resistive memory cell memory array.

Spatial correlation of reference cells in resistive memory array

A random number generator device that utilizes a magnetic tunnel junction. An AC current source is in electrical connection to the magnetic tunnel junction to provide an AC current having an amplitude and a frequency through the free layer of the magnetic tunnel junction, the AC current configured to switch the magnetization orientation of the free layer via thermal magnetization. A read circuit is used to determine the relative orientation of the free layer magnetization in relation to the reference layer magnetization orientation.

Tunable random bit generator with magnetic tunnel junction

Various embodiments of the present invention are generally directed to an apparatus and associated method for a non-volatile memory with a hybrid index tag array. In accordance with some embodiments, a memory device has a word memory array formed of non-volatile resistive sense memory (RSM) cells, a first index array formed of volatile content addressable memory (CAM) cells, and a second index array formed of non-volatile RSM cells. The memory device is configured to output word data from the word memory array during a data retrieval operation when input request data matches tag data stored in the first index array, and to copy tag data stored in the second index array to the first index array during a device reinitialization operation.

Non-volatile memory with hybrid index tag array

A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage, the magnetic tunnel junction data cell having a first resistance state and storing the first bit line read voltage in a first voltage storage device. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The second bit line read voltage is stored in a second voltage storage device. The method also includes comparing the first bit line read voltage with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.

Method and apparatus for writing data to a storage array, such as but not limited to an STRAM or RRAM memory array, using a read-mask-write operation. In accordance with various embodiments, a first bit pattern stored in a plurality of memory cells is read. A second bit pattern is stored to the plurality of memory cells by applying a mask to selectively write only those cells of said plurality corresponding to different bit values between the first and second bit patterns.

Data storage using read-mask-write operation

Resistive memory calibration for self-reference read methods are described. One method of self-reference reading a resistive memory unit includes setting a plurality of resistive memory units to a first resistive data state. The resistive memory units forms a memory array. Reading a sensed resistive data state for each resistive memory unit by applying a first read current and a second read current through each resistive memory unit and then comparing voltages formed by the first read current and the second read current to determine the sensed resistive data state for each resistive memory unit. Then the method includes adjusting the first or the second read current, read voltages, or storage device capacitance for each resistive memory unit where the sensed resistive data state was not the same as the first resistive data state until the sensed resistive data state is the same as the first resistive data state.

Resistive sense memory calibration for self-reference read method

Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction.

Write current compensation using word line boosting circuitry

An apparatus and method for enhancing read and write sense margin in a memory cell having a resistive sense element (RSE), such as but not limited to a resistive random access memory (RRAM) element or a spin-torque transfer random access memory (STRAM) element. The RSE has a hard programming direction and an easy programming direction. A write current is applied in either the hard programming direction or the easy programming direction to set the RSE to a selected programmed state. A read circuit subsequently passes a read sense current through the cell in the hard programming direction to sense the selected programmed state of the cell.

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Appl, MN, United States of America

Henry F Huang